FPGA SerDes Block Using Phase-Shifted Oversampling for USB 2.0
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Solution Overview
Problem
Conventional Field-Programmable Gate Arrays (FPGAs) face challenges in handling high-speed USB 2.0 data transmission due to limited capabilities in device connectivity and the need for a Clock Data Recovery (CDR) circuit, especially in handling the high-speed mode of USB 2.0.
Innovation Solution
A system comprising a host and an FPGA with configurable logic blocks, a USB interface, and a bus that includes P-channel and N-channel signals, utilizing differential comparators to identify logic zero states and facilitate high-speed data communication by oversampling data signals with clock frequencies twice that of the data rate, with a 90-degree phase shift, enabling efficient data transmission without the need for a CDR circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional FPGA uses GPIO to handle USB data transmission, then it can support low-speed and full-speed modes, but it cannot handle high-speed mode (480 Mbps)
Solution Approach 1:
The USB interface handling is segmented into different functional blocks: differential comparators for signal detection, input deserializers for high-speed data reception, and configurable logic blocks for protocol handling. This segmentation allows each component to be optimized for specific speed requirements while maintaining overall USB compatibility across low-speed, full-speed, and high-speed modes.
Solution Approach 2:
The FPGA employs dynamic configuration where the same physical interface can be reconfigured to handle different USB speed modes. The configurable logic blocks and deserializers can be activated or deactivated based on the detected USB mode, allowing the device to adapt its internal architecture dynamically to match the communication speed requirements.
2Speed
If an FPGA deploys a CDR circuit to handle high-speed USB mode, then it can achieve 480 Mbps transmission, but the device complexity increases
Solution Approach 1:
The patent extracts the clock data recovery function from a separate dedicated CDR circuit and integrates it into the input deserializer block. By combining the deserialization and clock recovery functions into a single unit, the design eliminates the need for a separate complex CDR circuit while still achieving high-speed data reception capability.
Solution Approach 2:
The input deserializer is merged with clock data recovery functionality, creating a unified block that performs both functions. This merging reduces the overall device complexity by eliminating redundant components and interconnections that would exist if CDR and deserialization were separate modules.
3Device complexity
If an FPGA uses a typical serdes without CDR circuit, then the device complexity is reduced, but it cannot handle high-speed USB mode
Solution Approach 1:
The input deserializer is designed with built-in oversampling capability that performs preliminary clock recovery and data sampling before the data reaches the configurable logic blocks. This preliminary action embedded in the deserializer enables high-speed operation without requiring a separate post-processing CDR stage.
Solution Approach 2:
The patent replaces the traditional mechanical/separate CDR circuit architecture with an integrated digital deserializer that performs clock recovery through oversampling and phase detection algorithms. This substitution eliminates complex analog CDR components while achieving the same high-speed data recovery function through digital signal processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed data communication between a host and FPGA, effectively handling USB 2.0 high-speed mode without requiring a CDR circuit, enhancing the flexibility and efficiency of FPGA devices in handling high-speed data transmissions.
Implementation Method 1
a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel
Implementation Method 2
a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel
Data Source
AI summary
A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.