Phase-Shifted Parallel-Serial Circuit for Low-Power Data Conversion
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Solution Overview
Problem
Conventional parallel to serial conversion circuits face issues with high power consumption and complexity due to the need for frequency multiplication or division, which is not effectively reduced in high-frequency environments, and can lead to inaccurate data conversion.
Innovation Solution
A parallel to serial conversion circuit utilizing a plurality of switching units with a phase shift and a common current source, where each switching unit receives a first and second clock signal of the same frequency, allowing all data bits to be converted within one clock period without the need for frequency multiplication or division, and ensuring stable tail current for accurate data conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency multiplication is used to convert parallel data to serial data, then data conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent divides the parallel data bus into multiple segments, with each segment handled by a dedicated switching unit. This segmentation allows simultaneous processing of multiple data bits across different segments, achieving high-speed serial conversion without requiring frequency multiplication. Each switching unit operates independently on its assigned data segment, enabling parallel-to-serial conversion at the original clock frequency.
Solution Approach 2:
The patent introduces a time dimension by utilizing phase-shifted clock signals to control different switching units at different time intervals. This temporal dimension allows multiple switching units to operate in a coordinated manner, effectively multiplying the conversion capacity without increasing the clock frequency. The phase-shifted clocks create a time-multiplexed operation that achieves high-speed conversion while maintaining low power consumption.
2Productivity
If frequency multiplication is used to achieve high-speed data conversion, then productivity is improved, but device complexity increases
Solution Approach 1:
The data bus is segmented into multiple portions, with each segment assigned to a dedicated switching unit. This segmentation enables simultaneous processing of multiple data bits without requiring complex frequency multiplication circuits. The segmented approach distributes the conversion workload across multiple simple switching units, maintaining low device complexity while achieving high productivity.
Solution Approach 2:
The patent combines multiple switching units with phase-shifted clock signals to achieve high-speed conversion. By merging the functionality of multiple simple switching units operating in parallel with time-multiplexed control, the system achieves the equivalent performance of a complex frequency-multiplying circuit but with simpler individual components and overall lower system complexity.
3Measurement precision
If multiple current sources are used for each switching unit, then data conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple current sources into a single shared current source that supplies all switching units. This shared current source is controlled by phase-shifted clock signals that ensure only one switching unit is active at any given time. By combining the current sources and using time-multiplexed control, the system maintains accurate data conversion (equivalent to having separate current sources) while significantly reducing power consumption through the shared current supply.
Solution Approach 2:
The patent employs periodic, phase-shifted clock signals to control the switching units in a sequential manner. Each switching unit is activated during its specific time window defined by the phase-shifted clock, ensuring that only one unit draws current from the shared current source at any moment. This periodic activation pattern maintains conversion accuracy while minimizing overall power consumption compared to having continuously active separate current sources.
Data Source
AI summary
A parallel to serial conversion circuit includes a plurality of switching units and a voltage output unit providing an operating voltage for the switching units. Each of the plurality of switching units is operable to receive a first clock signal and a second clock signal which have the same frequency, a phase shift exists between the first clock signal and the second clock signal for each of the switching units, and a phase difference exists between the first clock signals received by adjacent two switching units of the plurality of switching units. The plurality of switching units receive data bits of parallel data in sequence according to the phase difference, particularly, each of the plurality of switching units receives one data bit within a time window corresponding to the phase shift. In comparison with the prior art, the inventive solution implement the parallel to serial conversion using a single system clock frequency, so that the complexity and power consumption of the system is reduced.