Digital Phase Shifter Layout for Low-Loss High-Frequency Delay
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Solution Overview
Problem
The loss of high-frequency signals increases with frequency due to capacitance in digital phase shift circuits, leading to insufficient delay when capacitance is reduced.
Innovation Solution
A digital phase shift circuit design where the inner lines are positioned closer than 10 μm to the signal line, reducing capacitance while maintaining sufficient delay by increasing inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the capacitance value of the capacitor is decreased to reduce signal loss at high frequencies, then signal loss decreases, but the delay amount becomes insufficient
Solution Approach 1:
The patent changes the physical parameters of the transmission line structure by reducing the distance between inner lines and signal line to less than 10 μm. This structural parameter change increases inductance while allowing capacitance to be reduced, thereby resolving the contradiction between signal loss and delay amount
Solution Approach 2:
The patent employs a composite transmission line structure consisting of signal lines, inner lines, outer lines, and grounding conductors with specific geometric relationships. This composite structure enables simultaneous optimization of inductance and capacitance characteristics to resolve the technical contradiction
2Loss of time
If the inner lines are positioned closer to the signal line to increase inductance, then delay amount is maintained, but the circuit complexity increases
Solution Approach 1:
The patent resolves the complexity issue by transitioning to a planar transmission line geometry where the distance parameter (less than 10 μm) between conductors is optimized. This dimensional approach allows inductance control through geometric configuration rather than complex circuit topologies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases signal loss at high frequencies while limiting the decrease in delay amount, achieving a balance between signal integrity and circuit size.
Implementation Method 1
A delay amount in the digital phase shift circuit is proportional to the square root of the product of an inductance value and a capacitance value of the digital phase shift circuit
Implementation Method 2
The capacitor is connected between the signal line and the second grounding conductor
Data Source
AI summary
A digital phase shift circuit includes: a signal line extending in a predetermined direction; two inner lines disposed on both one side and another side of the signal line and separated a predetermined distance from the signal line; two outer lines provided at positions which are farther from the signal line than the inner lines on both the one side and the other side; a first grounding conductor electrically connected to one end of each of the inner lines and the outer lines; and a second grounding conductor electrically connected to other ends of the outer lines, and the predetermined distance is set to be less than 10 μm.