Phase-Modulated Signal Conversion with Dynamic Clock Phase Sampling
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Solution Overview
Problem
Existing phase modulation converters face challenges in achieving high resolution without reducing the modulator frequency, leading to larger filter components and increased costs, particularly when using fast FPGA architectures, and they require complex and expensive amplitude references.
Innovation Solution
The method involves dynamically changing the phase of the sampling clock signal to achieve increased resolution by dynamically changing the phase of the sampling clock signal, particularly by steps of less than 40°, preferably less than 20°, and most preferably by steps of less than 10°.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate is increased to achieve high resolution, then measurement precision is improved, but the modulator frequency must be reduced which increases filter component size and cost
Solution Approach 1:
The patent applies dynamics by making the sampling clock signal phase variable rather than fixed. The phase of the sampling clock is dynamically adjusted to optimize the measurement process, allowing high resolution to be achieved without reducing the modulator frequency. This dynamic phase adjustment enables the system to maintain both high resolution and high modulator frequency, avoiding the need for large filter components.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock signal to achieve the desired measurement precision. By varying the phase of the sampling clock rather than changing its frequency, the system can improve resolution while maintaining the modulator frequency at its original value, thus avoiding the trade-off that would otherwise require reducing modulator frequency and increasing filter size.
2Productivity
If fast FPGA architectures are used to achieve high sampling rates, then productivity is improved, but device complexity and cost increase
Solution Approach 1:
The patent uses dynamic phase adjustment of the sampling clock to achieve high effective sampling rates without requiring the highest possible clock frequencies. This dynamic approach allows the use of more modest FPGA architectures that can still achieve the required productivity through intelligent phase management rather than brute-force high-frequency sampling.
3Measurement precision
If the modulator frequency is reduced to increase resolution, then measurement precision is improved, but the data rate decreases
Solution Approach 1:
The patent changes the phase parameter of the sampling clock to achieve high resolution measurements. This parameter change allows the system to maintain high modulator frequency and thus high data rate, while still achieving the required resolution through phase-based optimization rather than frequency-based approaches.
Data Source
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AI summary
The invention relates to a method for converting an analog input signal (SigA) into a digital output signal (Sigo), comprising the steps: - the analog input signal (SigA) to be converted is fed to an amplitude modulator (2) with carrier suppression to obtain a carrierless amplitude-modulated signal (SigAM); - a 90° shifted, preferably sinusoidal carrier signal (SigT90) is added in an adder (7) to the amplitude-modulated (SigAM) signal output by the amplitude modulator (2) to obtain a phase-modulated signal (SigPM); - the phase-modulated signal (SigPM) is fed to a limiter (11) by means of which interference amplitude modulation in the phase-modulated signal (SigPM) is suppressed; - the signal output by the limiter (11) (SigBA) is fed to a demodulation device (16) supplied and sampled therein with at least one sampling clock signal (CLK0-CLK3),wherein - the phase of the at least one sampling clock signal (CLK0-CLK3) is dynamically changed to achieve increased resolution. Furthermore, the invention relates to a device (1) for converting an analog input signal into a digital output signal.