Phase Signal Encoding for Sub-Gate-Delay Time Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time-domain analog-to-digital converters in highly-scaled semiconductor technologies suffer from sampling errors due to delay mismatch between phase taps of cyclic coupled ring oscillators, which degrade performance and limit resolution and bandwidth.
Innovation Solution
A method and apparatus that encodes the sampled phase signal of cyclic coupled ring oscillators using a selective bit inversion and compression scheme, providing a unary code that is then unfolded to mitigate sampling errors, ensuring technology-independent sub-gate-delay resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cyclic coupled ring oscillators are used to achieve sub-gate-delay resolution, then time resolution is improved, but sampling errors due to delay mismatch between phase taps occur
Solution Approach 1:
The patent implements a feedback mechanism where the sampled phase signal is encoded into unary code, detected for validity, and corrected if erroneous. The correction logic uses feedback from the detection stage to identify and fix sampling errors caused by delay mismatch, ensuring reliable time resolution measurements even in deeply-scaled technologies where wire delay dominates gate delay
Solution Approach 2:
The patent converts the harmful effect of delay mismatch into a detectable pattern. By encoding the sampled phase signal into unary code, the system transforms sampling errors into identifiable invalid code patterns that can be detected and corrected. The harmful delay mismatch becomes a distinguishable error condition rather than an uncorrectable degradation
2Speed
If wire delay is reduced in highly-scaled semiconductor technology, then speed is improved, but delay mismatch between phase taps increases
Solution Approach 1:
The system performs self-diagnosis and self-correction of sampling errors through the encoding-detection-correction pipeline. The unary code encoding scheme enables the system to automatically identify when sampling errors have occurred due to delay mismatch, and the correction logic automatically fixes these errors without external intervention, making the system self-sufficient in compensating for manufacturing variations
Solution Approach 2:
The patent changes the parameter representation from direct binary phase values to unary code representation. This parameter transformation makes the system insensitive to delay mismatch variations, as the unary encoding scheme is inherently more robust to timing variations. The parameter change from binary to unary representation resolves the contradiction between speed and precision
3Productivity
If inverter delay is reduced to improve bandwidth, then productivity is improved, but time resolution dependent on inverter delay degrades
Solution Approach 1:
The patent transitions from relying on gate delay (time domain) to using phase sampling (phase domain) for time resolution. By sampling the phase signal at multiple points around the oscillator cycle and encoding into unary code, the system achieves time resolution that is independent of the inverter delay magnitude. This dimensional shift from gate-delay-based to phase-sampling-based resolution enables high bandwidth without sacrificing precision
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
An apparatus and a method for encoding a sampled phase signal. The apparatus receives an input from a sub-gate-delay resolution arrangement and has a processing circuitry configured to invert selectively a set of bits in a sampled matrix sampled at a sampling instance based on a first predefined reference node of the sub-gate-delay resolution arrangement in order to provide a unary code. The unary code is then compressed and used in unfolding a mapping based on the compressed unary code using a value of a chosen bit. Then the apparatus is provide an output based on said unfolding. As a result the arrangement provides a possibility to use a sub-gate-delay for several different applications.