Phase Skew Generator Using Current-Controlled Delay Stages
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Solution Overview
Problem
Generating precision phase skews using traditional delayed locked loops (DLLs) is difficult and expensive due to the requirement for a large number of delay line stages, which consumes significant IC space and requires complex circuitry, affecting accuracy and power consumption.
Innovation Solution
A phase skew generator with an enhanced charge pump, capacitor, sample and hold circuit, and voltage-controlled delay line (VCDL) with only four delay line stages, where the delay time is adjusted by controlling the current and operation regions to achieve precision phase skews, reducing the number of stages and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of delay line stages are used in the VCDL to generate precision phase skews, then the phase skew accuracy is improved, but the IC space consumption and device complexity increase significantly
Solution Approach 1:
The patent changes the operating parameters of the delay line stages by controlling the charge and discharge currents of a capacitor to adjust the delay time. By varying current magnitudes during different time periods, the system achieves precise phase skew control without increasing the number of delay stages, thus maintaining accuracy while reducing IC space consumption.
Solution Approach 2:
The patent employs periodic charging and discharging of a capacitor through controlled current paths during different time periods. This periodic action allows the delay time to be dynamically adjusted in a cyclic manner, enabling precision phase skew generation with fewer delay stages by utilizing time-domain control rather than spatial expansion.
2Measurement precision
If the number of delay line stages is increased to achieve precision phase skews, then the phase skew accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent achieves precise phase skew control by changing current parameters dynamically. By controlling the magnitude and duration of charge/discharge currents to a capacitor, the system adjusts delay time without requiring additional delay stages, thereby maintaining measurement precision while significantly reducing power consumption associated with extra circuitry.
Solution Approach 2:
The system transitions from a static delay line structure to a dynamic control mechanism where delay time is adjusted by varying current parameters over time. This dynamic approach allows the same hardware to achieve multiple delay values, reducing the need for additional static delay stages and their associated power consumption.
3Adaptability or versatility
If a multiplexer is added to select delay stages in a configurable VCDL, then the adaptability is improved, but the measurement precision deteriorates due to significant multiplexer delay time
Solution Approach 1:
The patent removes the multiplexer component from the system entirely. Instead of using a multiplexer to select delay stages, the invention extracts the selection function and implements it through direct control of charge/discharge current paths to a capacitor. This eliminates the harmful multiplexer delay time while maintaining configurability through current-controlled delay adjustment.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element between the current sources and the delay line. This capacitor mediates the delay control by being charged or discharged through controlled current paths, allowing the system to achieve configurable delay times without the need for a multiplexer, thus maintaining both adaptability and measurement precision.
Data Source
AI summary
A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.