Phase-Skipping DLL for High-Frequency Multi-Phase Clock Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loop (DLL) circuits face limitations in achieving high-speed and high-phase number operations due to constraints on delay performance, size, power consumption, design complexity, and the need for complex calibration or synchronization, particularly when trying to generate multiple clock phases from a single phase or differential pair of phases.
Innovation Solution
The proposed solution involves modifying the conventional operation of a M-phase DLL by allowing the delays of each delay cell to be multiples of the DLL unit intervals, relaxing the performance requirements, and enabling the DLL to lock to different phases of the input clock period, including multiples of the input clock, by removing the restriction that outputs of consecutive delay stages must be consecutive clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the delays of each delay cell are set to multiples of the DLL unit intervals (k*Δt), then the performance requirements of each delay cell are relaxed and high-frequency operation is enabled, but the outputs of consecutive delay stages are no longer consecutive clock phases requiring phase reordering
Solution Approach 1:
The patent applies phase skipping by allowing delay cells to skip intermediate clock phases and directly produce phases separated by k unit intervals. This enables the DLL to operate at higher frequencies by effectively 'rushing through' intermediate phases rather than sequentially generating each phase, thus resolving the contradiction between speed and complexity
Solution Approach 2:
The patent changes the delay parameter from the conventional single unit interval (Δt) to multiple unit intervals (k*Δt). This parameter change allows each delay cell to produce larger phase jumps, enabling high-frequency operation while the alignment circuit compensates for the non-consecutive phase output through intelligent phase reordering
2Adaptability or versatility
If the DLL is designed to lock to different phases of the input clock period (false locking region), then high phase number and high frequency operation is enabled, but conventional design restrictions must be removed
Solution Approach 1:
The patent inverts the conventional approach by intentionally designing the DLL to lock in the false locking region (different phases) rather than avoiding it. This inversion transforms a previously problematic design region into a useful operating mode, enabling high phase number and high frequency operation while managing the associated design complexities through systematic phase reordering
3Quantity of substance
If independent delay lines are used to achieve high phase number, then phase generation capability is improved, but asymmetrical delay elements impact overall matching of output clock phases
Solution Approach 1:
The patent merges multiple delay lines into a unified structure where all delay cells share the same delay characteristic (k*Δt). This consolidation ensures that all output phases, regardless of which delay line they originate from, maintain consistent timing relationships and can be properly reordered by the alignment circuit, thus improving phase matching precision while maintaining high phase number capability
Data Source
AI summary
A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*Δt, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.