Phase Synchronization Circuit With Calibration for Low-Jitter Clocks
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Solution Overview
Problem
Existing voltage controlled oscillators face frequency fluctuations due to manufacturing or use conditions, leading to unstable oscillation frequencies, which affect the precision of clock signals in phase synchronization circuits.
Innovation Solution
A phase synchronization circuit is designed with a variable current generation unit and a fixed current generation unit, along with a feedback circuit and control voltage generation circuit, to generate a high-precision output clock signal. The circuit includes a calibration mode to adjust a correction code, ensuring a stable frequency relationship between feedback and reference clock signals, thereby stabilizing the oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an offset current is added to provide a base oscillation frequency, then the oscillation frequency can be established, but the oscillation frequency fluctuates due to manufacturing or use conditions
Solution Approach 1:
The patent applies dynamics by making the offset current adjustable through a correction code input terminal. The offset current generation circuit can dynamically adjust the offset current magnitude based on the correction code, allowing the system to adapt to manufacturing variations and use conditions, thereby resolving the frequency stability issue caused by fixed offset current precision limitations
Solution Approach 2:
The patent changes the parameter of offset current by introducing a correction code that controls the offset current generation circuit. This allows the offset current magnitude to be modified according to actual frequency deviation, enabling frequency calibration and compensation for manufacturing tolerances, thus improving oscillation frequency stability
2Speed
If a voltage controlled oscillator is used to generate clock signals, then frequency control is achieved, but frequency fluctuations and jitter occur in the output clock signal
Solution Approach 1:
The patent implements feedback by comparing the phase of the output clock signal with a reference clock signal and generating a control signal based on the phase difference. This control signal adjusts the offset current to compensate for frequency deviations, creating a closed-loop system that reduces frequency fluctuations and jitter while maintaining frequency control capability
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the offset current based on the correction code before the frequency deviation becomes significant. The calibration circuit proactively compensates for known manufacturing variations, preventing frequency drift rather than merely reacting to it, thus improving overall frequency stability
Data Source
AI summary
A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.