Phase Synchronization Circuit With Jitter-Monitored Delay Control
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Solution Overview
Problem
Phase locked loop circuits experience jitter in output clock signals due to power supply noise interference, particularly when multiple circuits operate simultaneously, making it difficult to maintain stable clock signals.
Innovation Solution
Incorporating a delay circuit that adjusts its delay amount to minimize jitter by monitoring and controlling the phase of the reference clock signal, thereby reducing the impact of power supply noise on the output clock signals. This is achieved through an analog-digital converter and a delay control circuit that varies the delay amount to optimize the phase alignment and reduce variations in the clock control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple phase locked loop circuits operate simultaneously, then productivity increases, but jitter in output clock signals increases due to power supply noise interference
Solution Approach 1:
The patent segments the power supply noise affecting multiple phase locked loop circuits into individual manageable units by providing a separate delay circuit for each circuit. Each delay circuit independently adjusts its delay amount to minimize jitter in its respective output clock signal, allowing multiple circuits to operate simultaneously without mutual interference degradation.
Solution Approach 2:
The patent changes the delay parameter of each delay circuit dynamically to minimize jitter. The delay control circuit adjusts the delay amount based on monitored jitter levels, effectively changing the timing parameter to counteract power supply noise effects and maintain stable clock signals across multiple operating circuits.
2Reliability
If a delay circuit adjusts delay amount to minimize jitter, then clock signal stability improves, but device complexity increases
Solution Approach 1:
The patent implements feedback by having the monitoring circuit continuously monitor jitter in the output clock signal and feed this information back to the delay control circuit. The delay control circuit then adjusts the delay amount based on this feedback to minimize jitter, creating a closed-loop control system that automatically maintains clock signal stability.
Solution Approach 2:
The delay circuit system serves itself by automatically adjusting its own delay parameter based on monitored jitter conditions. The monitoring circuit detects jitter, the delay control circuit processes this information, and the delay circuit self-corrects its delay amount without external intervention, enabling autonomous jitter minimization.
Data Source
AI summary
A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.