Phase Synchronization Circuit Current Matching
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in maintaining synchronization due to variations in bias current values of charging and discharging currents, leading to instability and difficulty in accurately matching current values across multiple PLLs, especially due to production variations and parasitic capacitance effects.
Innovation Solution
A phase synchronization circuit with a charging/discharging circuit, an oscillation circuit, and a setting circuit that adjusts current values to maintain a constant charging voltage, using a drive circuit to match charging and discharging periods and adjust current mismatches, ensuring accurate synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bias current values of current sources I1 and I2 are made identical through design, then the charging and discharging current values should be matched, but production variations make it difficult to achieve identical current values
Solution Approach 1:
The patent implements a feedback mechanism where the charging voltage of capacitor C is monitored and fed back to control the bias current adjustment circuit 440. The adjustment circuit modifies the bias current values of current sources I1 and I2 based on the charging voltage feedback, creating a closed-loop system that automatically compensates for current mismatches caused by production variations, thereby achieving accurate current matching and reliable PLL synchronization.
Solution Approach 2:
The patent dynamically adjusts the bias current parameters of current sources I1 and I2 through the bias current adjustment circuit 440. By changing the bias current values based on charging voltage feedback, the system adapts to production variations and achieves matched charging/discharging currents, resolving the contradiction between manufacturing precision and reliability.
2Stability of the object's composition
If switches SW1 and SW2 are turned on for the same periods to maintain constant charging voltage, then PLL locked state is maintained, but parasitic capacitance prevents switch SW1 from turning on when charging voltage is reduced
Solution Approach 1:
The patent applies preliminary anti-action by proactively adjusting the bias current values of current sources I1 and I2 before the parasitic capacitance effect becomes critical. The feedback mechanism detects charging voltage trends and preemptively modifies current values to ensure switch SW1 can reliably turn on, preventing the harmful effect of parasitic capacitance from disrupting PLL operation.
Solution Approach 2:
The system provides beforehand cushioning by maintaining a sufficient margin in the bias current values through continuous feedback adjustment. This ensures that even when charging voltage is reduced, the current sources have enough driving capability to overcome parasitic capacitance effects and reliably switch, thus cushioning against potential operation failures.
3Manufacturing precision
If arbitrary number of PLLs are extracted as samples to set bias current adjustment, then current matching can be achieved in typical PLLs, but it is difficult to accurately match current values in non-sampled PLLs
Solution Approach 1:
The patent implements a universal feedback-based bias current adjustment mechanism that functions across all PLLs regardless of whether they were sampled during manufacturing. The charging voltage feedback and automatic adjustment system provides multi-functional capability, ensuring accurate current matching in both sampled and non-sampled PLLs, thus achieving universality.
Solution Approach 2:
Each PLL equipped with the feedback mechanism becomes self-sufficient in achieving current matching. The charging voltage feedback automatically guides the bias current adjustment without requiring external sampling or manual calibration, enabling every PLL to self-adjust and achieve accurate current matching independently.
Data Source
AI summary
A phase synchronization circuit comprising: a charging/discharging-circuit to charge/discharge a capacitor in accordance with a drive-signal, charging and/or discharging current-values of the capacitor being settable; an oscillation-circuit to output an oscillation-signal having a frequency corresponding to a charging-voltage; a drive-circuit to output as the drive-signal a first drive-signal for matching charging and discharging periods when a phase-difference and the oscillation-signal is smaller than a predetermined phase-difference and reducing the phase-difference when the phase-difference is greater than the predetermined phase-difference; and a setting-circuit to receive setting-data for setting the charging and/or discharging current-values, hold the setting-data, and set the charging and/or discharging current-values, based on the setting-data, the drive-circuit outputting as the drive-signal a second drive-signal for matching charging and discharging periods, when receiving an adjustment-instruction-signal, the setting-circuit holding the setting-data for rendering at a constant level the charging-voltage of the capacitor charged/discharged in accordance with the second drive-signal.