Phase Value Transfer Circuit for Non-Synchronous Clock Domains
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Solution Overview
Problem
There is a need for circuits to reliably transfer n-bit phase values between systems clocked by non-synchronous clock signals, particularly for applications involving counters and frequency synthesizers, where the phase values must adhere to setup and hold requirements at each clock edge, and existing solutions require additional synchronization and replication of phase information.
Innovation Solution
A circuit comprising a phase and marker signal generator, a latching clock delay circuit, an n-bit variable phase delay circuit, and phase and marker flip-flops, which generates and transfers n-bit phase values by accumulating a frequency control word, setting delays based on the phase value and fixed periods, and generating edge signals to synchronize phase transfers across non-synchronous clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional synchronization circuits are used to transfer phase values between non-synchronous clock domains, then reliability of phase value transfer is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the required delay value in a lookup table before the actual phase value transfer occurs. The system determines the clock domain relationship in advance and prepares the corresponding delay parameter, which is then applied during the transfer operation. This eliminates the need for complex real-time synchronization circuits while ensuring reliable phase value transfer between non-synchronous clock domains.
2Reliability
If phase information is replicated across clock domains, then reliability of phase value transfer is improved, but use of energy increases
Solution Approach 1:
The patent extracts only the essential phase value parameter from the original phase information and transfers only this extracted data between clock domains. Instead of replicating entire phase signals or using complex synchronization mechanisms that consume significant power, the system isolates and transfers merely the numerical phase value through a simple delay adjustment mechanism, thereby dramatically reducing power consumption while maintaining transfer reliability.
3Measurement precision
If complex synchronization mechanisms are implemented, then measurement precision of phase value transfer is improved, but device complexity increases
Solution Approach 1:
The patent changes the approach from using complex synchronization mechanisms to adjusting a single critical parameter: the delay time. By dynamically modifying the delay parameter based on the relationship between source and destination clock domains, the system achieves accurate phase value transfer. The delay value is calculated based on clock frequency ratios and used to adjust the timing of phase value latching, thereby achieving measurement precision without complex circuitry.
Data Source
AI summary
A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.