Phase Vocoder DSP Engine with Pi-Mapping for Streaming Media

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Solution Overview

Problem

Modern digital signal processing of streaming audio and video data is resource and power hungry, leading to inefficiencies that increase end-to-end latency and result in undesirable user-perceivable artifacts due to cumulative floating point errors and high processor load.

Innovation Solution

Implementing a phase vocoder with Pi-mapping for spectrally-binned output and complex-to-polar transforms, along with an optimization engine to eliminate processor stalls and an algorithm selection engine to optimize algorithm usage, significantly reduces processing time and resource consumption while minimizing cumulative phase errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional DSP implementations are used with general purpose or special purpose processors, then platform neutrality and forward/reverse compatibility are achieved, but resource consumption and power consumption increase substantially

Engineering Contradiction:

Improveplatform neutralityVSAvoidCPU and memory bus budget consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces traditional software-based DSP processing on general purpose processors with a hardware-accelerated DSP engine that implements optimized signal processing algorithms. This substitution of mechanical/software system with a dedicated hardware system reduces resource consumption while maintaining processing capabilities.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the implementation parameters by moving from software execution to hardware implementation, and by optimizing the DSP algorithms to use fixed-point arithmetic instead of floating-point arithmetic. This parameter change reduces computational complexity and resource consumption while maintaining processing accuracy.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If traditional DSP processing is used, then comprehensive signal processing functionality is achieved, but end-to-end latency increases

Engineering Contradiction:

Improvesignal processing functionalityVSAvoidend-to-end latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent replaces software-based processing with hardware-accelerated processing, which executes signal processing operations faster and reduces end-to-end latency while maintaining comprehensive signal processing functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements pre-computation and optimization of signal processing algorithms during the design phase, creating optimized instruction sequences and data flow paths that reduce processing latency when the system operates.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If traditional DSP implementations are used, then processing coverage is maintained, but cumulative floating point errors and processor load increase

Engineering Contradiction:

Improveprocessing coverageVSAvoidfloating point error accumulation

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point to fixed-point arithmetic, which eliminates cumulative floating-point errors while maintaining sufficient processing precision for audio and video signal processing applications.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10108425B1High-efficiency digital signal processing of streaming media

Publication Date: 2018.10.23 DISTRIBUTED CREATION INC

AI summary

A computing device reorders an iteratively executed sequence of instructions such that constituent instructions that require longer execution time than other constituent instructions are grouped together. The computing device inserts, within the iteratively executed sequence of instructions, one or more additional instructions to enable parallel execution of two or more instances of the sequence of instructions such that the constituent instructions that require longer execution time will be executed concurrently with the other constituent instructions.