Time-Interleaved Phased Array Receivers With Randomized ADC Sampling

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Solution Overview

Problem

Conventional phased array receivers face limitations due to errors caused by offset, gain error, clock-skew, finite bandwidth mismatches, and other non-ideal effects between analog-to-digital converters, which affect signal processing and noise performance.

Innovation Solution

The implementation of time interleaved analog-to-digital converters with random or pseudo-random sampling sequences, where the sampling by sub-analog-to-digital converters is random within and between compound converters, effectively spreads error energy across the noise floor, reducing correlated noise and improving signal-to-noise ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional analog-to-digital converters are used in phased array receivers, then signal conversion is achieved, but channel mismatch errors (offset, gain error, clock-skew, finite bandwidth mismatches) degrade signal-to-noise ratio

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidchannel mismatch errors
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The system divides the signal processing into multiple parallel analog-to-digital converter channels, each processing a portion of the phased array input signals. By segmenting the conversion process across multiple converters operating in parallel, the system can apply individual calibration to each channel, thereby reducing the impact of channel mismatch errors while maintaining overall signal-to-noise ratio performance.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple analog-to-digital converters are used to process phased array signals, then conversion capacity is increased, but channel mismatch errors between converters accumulate

Engineering Contradiction:
Improvesignal conversion capacityVSAvoidchannel mismatch errors
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system implements a calibration mechanism that measures the channel mismatch errors between multiple analog-to-digital converters and applies corrective feedback signals. The calibration process determines offset, gain, and timing differences between converters and generates compensation signals that are applied during normal operation, thereby eliminating the accumulation of channel mismatch errors while maintaining high conversion capacity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts operational parameters of the analog-to-digital converters, including sampling timing, gain settings, and offset levels, to optimize performance and minimize channel mismatch effects. By changing these parameters based on calibration data and operating conditions, the system maintains high conversion capacity while reducing error accumulation across multiple converters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12237857B2Time interleaved phased array receivers
Publication Date: 2025.02.25 ADESTO TECHNOLOGIES CORP
  • US12237857B2 patent drawing
  • US12237857B2 patent drawing
  • US12237857B2 patent drawing

AI summary

A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub-analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between the plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.