Phased Array Antenna Signal Processing Ring Architecture

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Solution Overview

Problem

Current digital beam forming in phased array antennas is computationally intensive and inflexible, leading to high processing and communication loads, especially as the number of antenna elements increases, making existing systems poorly scalable.

Innovation Solution

A phased array antenna signal processing structure with a ring structure of processors that distribute processing capacity and communication load by generating and adding partial beam data, allowing for equal loading of all processors and linear scalability with the number of antenna elements, while minimizing communication load and enabling hierarchical beam forming without a hierarchical processor structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If digital beam forming is performed using a central processor, then beam forming functionality is achieved, but processing load and communication load on the central processor become excessively high

Engineering Contradiction:
Improvebeam forming capabilityVSAvoidprocessing load
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent divides the central processor into multiple distributed processors arranged in a ring structure. Each processor handles a subset of antenna elements and performs partial beam forming operations. The ring structure allows intermediate results to be passed sequentially between processors, distributing the computational load and avoiding the bottleneck of a single central processor.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the number of antenna elements increases, then antenna array capability is improved, but computational requirements of the processor increase exceptionally

Engineering Contradiction:
Improvenumber of antenna elementsVSAvoidcomputational requirements
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system segments the antenna elements into groups, with each processor handling a specific subset. This allows the system to scale to a large number of antenna elements by simply adding more processors to the ring, rather than increasing the capacity of a single processor. The computational complexity per processor remains manageable while the overall system capability scales linearly with the number of processors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a spatial dimension to the processing architecture by arranging processors in a ring structure that physically or logically corresponds to the antenna element groups. This dimensional organization allows efficient distribution of computational tasks and data flow, reducing the complexity burden on individual processors while handling large numbers of antenna elements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If more processors are added to increase processing capacity, then processing capability is improved, but communication load between processors increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidcommunication load
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The ring structure segments the data flow into sequential segments, where each processor passes only its computed intermediate results to the next processor in the ring. This segmented approach minimizes the amount of data that needs to be communicated at each stage, as opposed to a fully connected architecture where every processor would need to exchange data with every other processor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ring structure acts as an intermediary data transmission path, where intermediate beam forming results are passed sequentially through the ring. This intermediary structure reduces communication overhead by providing a dedicated, efficient path for data flow that scales linearly with the number of processors, rather than requiring quadratic communication channels.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If a hierarchical beam forming structure is implemented, then processing efficiency is improved, but processor structure complexity increases

Engineering Contradiction:
Improvebeam forming efficiencyVSAvoidprocessor structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements hierarchical beam forming functionality through segmentation of processing tasks across identical processors in the ring. Each processor performs the same type of operations on its assigned antenna elements, and the hierarchical effect emerges from the sequential combination of intermediate results through the ring, rather than from a complex hierarchical processor architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

All processors in the ring are identical and universal, capable of performing the same beam forming operations on their assigned antenna elements. This universality simplifies the processor structure while still achieving hierarchical processing efficiency, as the same processor design can be replicated and configured for different processing levels through software or data routing rather than hardware hierarchy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2550706B1A phased array antenna signal processing structure, a method and a computer program product
Publication Date: 2019.05.08 NEDERLANDSE ORG VOOR TOEGEPAST NATUURWETENSCHAPPELIJK ONDERZOEK TNO
  • EP2550706B1 patent drawingFigure 1
  • EP2550706B1 patent drawingFigure 2
  • EP2550706B1 patent drawingFigure 3

AI summary

The invention relates to a phased array antenna signal processing structure. The structure comprises a processor that includes a digital beam forming unit for generating partial beam data from digitized samples of a set of phased array antenna elements. The processor further comprises a set of input terminals for receiving intermediate beam data from another processor. The processor also comprises an adder for generating new intermediate beam data by adding partial beam data generated by the digital beam forming unit to corresponding received partial beam data. In addition, the processor comprises a set of output terminals for transmitting the new intermediate beam data.