Physical Hardware Clock Chaining for Network Synchronization
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Solution Overview
Problem
Existing methods for synchronizing real-time clocks in computer networks face challenges due to latency and jitter, particularly when transferring clock synchronization signals between network interface controllers, which can be costly and inefficient, especially when trying to transfer PTP synchronization from a synchronized network to a non-synchronized network.
Innovation Solution
The solution involves connecting network interface controllers via coaxial radio-frequency (RF) cables to synchronize time values, with one controller acting as a master clock to provide frequency and phase information to another, allowing the second controller to act as a PTP master for its network, using marking pulses to encode and decode synchronization signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock synchronization messages are distributed among network nodes using standard network protocols, then clock synchronization can be achieved across network segments, but latency and jitter degrade the precision of synchronization
Solution Approach 1:
The system segments the clock synchronization function by introducing boundary clocks that separate different network segments. Each boundary clock maintains independent PHCs for different segments, allowing synchronization to be handled locally at segment boundaries rather than requiring end-to-end message passing across the entire network, thus reducing latency and jitter.
Solution Approach 2:
Boundary clocks act as intermediary devices between network segments. They receive synchronization references from upstream segments and generate synchronized time for downstream segments, mediating the synchronization process to prevent direct message passing between distant nodes and thereby reducing synchronization latency and jitter.
2Reliability
If a network interface controller has only one hardware clock for the entire device, then device complexity is reduced, but precise synchronization across multiple network ports cannot be achieved
Solution Approach 1:
The hardware clock function is segmented by providing separate PHCs for different network ports or functions within the same NIC. This allows each port to maintain independent precise time references while still being part of the same physical device, achieving port-level synchronization precision without requiring fully distributed clock architectures.
3Adaptability or versatility
If PTP synchronization is transferred from a synchronized network to a non-synchronized network using standard network messaging, then network connectivity is maintained, but synchronization accuracy degrades due to network latency and jitter
Solution Approach 1:
A boundary clock acts as an intermediary between the PTP-synchronized network and the non-PTP network. It receives accurate synchronization references from the PTP network and generates corresponding synchronized time for the non-PTP network using its local PHC, thereby maintaining synchronization accuracy while adapting to different network types without relying on message passing across the non-PTP network.
Solution Approach 2:
The system replaces software-based PTP messaging protocols with hardware-based PHC synchronization. By using dedicated hardware clocks and direct hardware connections (such as coaxial RF cables) for clock signal distribution, the system eliminates the latency and jitter inherent in software message passing, achieving nanosecond-level precision even when bridging different network types.
Data Source
AI summary
In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.