PHC Frequency Adjustment via Physical Layer Symbol Rates
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Solution Overview
Problem
Current clock synchronization methods, such as PTP, face challenges in maintaining accuracy and stability, especially when PTP messages are not available, leading to drift and reduced synchronization accuracy, and require costly hardware like jitter attenuators for SyncE, which is not feasible for all deployments.
Innovation Solution
The system adjusts Precision Time Protocol (PTP) Hardware Clock (PHC) frequency based on physical layer frequency information extracted from RX symbol rates, using a digital phase-locked loop (DPLL) to maintain accurate and stable clock synchronization without the need for additional hardware, by calculating an ensemble time from multiple network elements' symbol rates and adjusting the PHC accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PTP messages are used for clock synchronization, then time synchronization accuracy is improved, but the system becomes unreliable when PTP messages are not available
Solution Approach 1:
The patent introduces an intermediary mechanism (phase-locked loop and frequency adjustment circuitry) that translates physical layer signal characteristics into clock synchronization adjustments. This intermediary allows the system to derive synchronization information from the physical layer signal itself rather than relying solely on external PTP messages, thereby maintaining reliability when messages are unavailable.
Solution Approach 2:
The system performs self-service by extracting synchronization information from its own received physical layer signals. The phase-locked loop uses the incoming signal's timing characteristics to automatically adjust the local clock frequency, enabling the system to maintain synchronization autonomously without continuous external PTP messaging.
2Stability of the object's composition
If SyncE hardware (jitter attenuators) is used to maintain clock stability, then clock stability is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces complex mechanical/jitter-attenuation hardware with a digital/software-based phase-locked loop and frequency adjustment algorithm. Instead of using physical jitter attenuators to stabilize the clock, the system uses digital signal processing to detect and correct frequency deviations based on physical layer signal characteristics, thereby achieving clock stability without additional complex hardware.
Solution Approach 2:
The system changes the operating parameters of the clock by dynamically adjusting its frequency based on detected physical layer signal characteristics. The phase-locked loop continuously monitors signal timing and modifies the clock's frequency parameter in real-time to maintain synchronization, replacing static hardware stabilization with dynamic parameter adjustment.
3Measurement precision
If PTP Hardware Clock frequency is adjusted based on PTP messages, then time synchronization is improved, but frequency drift occurs when messages are unavailable
Solution Approach 1:
The patent ensures continuity of useful action by implementing a phase-locked loop that continuously monitors the physical layer signal and continuously adjusts the clock frequency. This continuous feedback mechanism eliminates gaps in synchronization control that would occur when PTP messages are unavailable, maintaining both time synchronization accuracy and frequency stability through uninterrupted operation.
Solution Approach 2:
The system implements a feedback mechanism where the phase-locked loop continuously detects timing deviations in the received physical layer signal and feeds this information back to adjust the clock frequency. This closed-loop feedback ensures that frequency drift is corrected in real-time, maintaining both synchronization accuracy and stability even when external PTP messages are unavailable.
Data Source
AI summary
A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.