pHEMT Low-Temperature Buffer Layer Mitigates Drain Lag
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power amplifiers constructed with existing pHEMT technologies suffer from drain and gate lag, kink effects, and other non-idealities due to deep level traps in the substrate and buffer layer, which impede rapid changes in drain voltage and impact amplifier performance.
Innovation Solution
A pHEMT device with a low-temperature buffer layer grown at a low temperature, incorporating a high concentration of 'fast' traps and microprecipitates that shield carriers from deep level traps, reducing lattice mismatch and improving resistivity, thereby mitigating drain lag and kink effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional buffer layer is used in pHEMT, then the device structure is simple, but deep level traps cause drain lag and kink effects
Solution Approach 1:
The buffer layer is segmented into multiple distinct layers: a low-temperature buffer layer (LTBL) grown at 300-500°C and a high-temperature buffer layer (HTBL) grown at 600-700°C. This segmentation allows each layer to perform specific functions - the LTBL provides fast traps to compensate for substrate deep level traps, while the HTBL provides lattice matching and low resistance, thereby reducing drain lag without excessive complexity
Solution Approach 2:
Different regions of the buffer structure are given different properties: the LTBL has high trap concentration and specific carrier concentration (10^16 to 10^18 cm^-3) to address deep level trap issues locally, while the HTBL has optimized thickness (0.5-2.0 μm) and doping for overall device performance. This local quality differentiation targets specific problems in different buffer regions
2Manufacturing precision
If the buffer layer is grown at high temperature, then the growth rate is fast, but lattice mismatch increases causing defects
Solution Approach 1:
The buffer growth is segmented into two temperature stages: LTBL grown at lower temperature (300-500°C) for better lattice matching and lower defect density, followed by HTBL grown at higher temperature (600-700°C) for faster growth rate. This temporal and spatial segmentation of growth conditions optimizes both lattice matching precision and manufacturing productivity
Solution Approach 2:
The LTBL is grown first as a preliminary layer to establish a low-defect foundation with good lattice matching. This preliminary action prepares the substrate for subsequent HTBL growth, ensuring that the faster high-temperature growth occurs on a pre-conditioned surface that minimizes defect propagation
3Reliability
If deep level traps are present in the substrate, then the device structure remains simple, but drain lag and kink effects occur
Solution Approach 1:
The invention converts the harmful deep level traps in the substrate into a benefit by intentionally introducing fast traps in the LTBL that compensate for the slow deep level traps. The harmful substrate traps are not removed but are counterbalanced by the engineered fast traps, transforming the problem into a solution while maintaining substrate simplicity
Solution Approach 2:
The LTBL acts as an intermediary layer between the substrate and the active device regions. It mediates the interaction between substrate deep level traps and channel carriers by providing fast traps that rapidly capture and release carriers, preventing the slow transient effects of substrate traps from reaching the active regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pHEMT device exhibits improved performance by reducing drain lag and kink effects, enabling efficient operation under dynamic drain bias conditions with faster response times and enhanced power amplifier performance.
Implementation Method 1
incorporating a high concentration of 'fast' traps and microprecipitates that shield carriers from deep level traps
Data Source
AI summary
A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.