PHEMT Gate Fabrication via Double Recess Etching
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Solution Overview
Problem
Conventional methods for fabricating pseudomorphic high electron mobility transistors (PHEMTs) face challenges in accurately controlling the linewidth of gate electrodes, leading to increased source resistance, gate resistance, and capacitance, which degrade electrical characteristics and limit high-frequency and high-speed performance.
Innovation Solution
A method involving the use of protective silicon nitride or silicon oxide layers for precise etching to form double recess structures, preventing active region exposure and enabling the formation of gate electrodes with minimized linewidth and reduced resistance, achieved through anisotropic etching and multilayered photoresist patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching process is used to form double recess structure, then etching is easier to perform, but linewidth control of gate electrode becomes inaccurate and lateral surfaces are etched
Solution Approach 1:
A protective layer is introduced as an intermediary between the wet etching process and the GaAs capping layer. This protective layer prevents the wet etching solution from directly contacting and etching the lateral surfaces of the GaAs capping layer, while allowing controlled etching of the AlGaAs layer through selective removal of the protective layer in recess regions.
Solution Approach 2:
The protective layer is selectively removed in the recess regions to expose the AlGaAs layer for etching, while maintaining coverage over the lateral surfaces of the GaAs capping layer. This creates locally different etching conditions: aggressive etching in recess areas and protected conditions for lateral surfaces, thereby achieving precise linewidth control.
2Ease of manufacture
If wet etching process is used to form double recess structure, then etching process is simpler, but active region is exposed and oxidized degrading electrical characteristics
Solution Approach 1:
The protective layer serves as a barrier that prevents direct exposure of the active region to the wet etching solution and ambient air during subsequent processing. By maintaining this protective barrier over the active region, oxidation is prevented and electrical characteristics are preserved.
Solution Approach 2:
The protective layer is applied beforehand to prevent the harmful oxidation of the active region before it can occur. This preliminary protective action ensures that even when the structure is exposed to air or moisture during processing, the active region remains protected from degradation.
3Ease of manufacture
If wet etching process is used to form double recess structure, then etching is more straightforward, but undercut is formed increasing gate electrode length and source resistance
Solution Approach 1:
The protective layer acts as a mask that prevents undercut formation by blocking the wet etching solution from attacking the underlying layers laterally. The etching is confined to vertically downward direction only, preventing the formation of undercuts that would increase gate electrode length and source resistance.
4Ease of manufacture
If photolithography process is used to form gate electrode, then manufacturing is simpler, but resolution limit prevents fine linewidth formation
Solution Approach 1:
The patent replaces the optical-based photolithography process with electron beam lithography. This substitution enables much finer linewidth control and higher resolution in defining the gate electrode pattern, overcoming the diffraction limit inherent in optical methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown voltage, reduces source and gate resistances, and minimizes capacitance, resulting in improved electrical characteristics and high-frequency capabilities for PHEMTs, suitable for high-speed and high-frequency applications.
Implementation Method 1
preventing active region exposure and oxidation
Implementation Method 2
achieved through anisotropic etching and multilayered photoresist patterning
Data Source
AI summary
Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.