Phosphorus-Doped Gate Insulating Layer for TFT Leakage Current Reduction
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Solution Overview
Problem
Thin film transistors in active matrix liquid crystal displays suffer from high leakage currents due to the characteristics of amorphous silicon, leading to image quality issues such as crosstalk and reduced durability.
Innovation Solution
A thin film transistor array substrate is developed with a phosphorus-doped gate insulating layer adjacent to the active layer, reducing hole current flow and increasing the on/off current ratio by obstructing hole flow while allowing electron flow, thereby reducing off-current and enhancing image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used to form the active layer, then the manufacturing cost is reduced and the formation process is simplified, but the leakage current increases due to hole current in the off-region
Solution Approach 1:
The patent applies local quality by creating a phosphorus-doped layer specifically at the gate insulating layer adjacent to the active layer channel. This localized doping modifies only the critical interface region where hole current originates, while maintaining the overall amorphous silicon structure and simple manufacturing process. The phosphorus doping concentration is specifically controlled in this local region to suppress hole current without affecting the bulk material properties.
Solution Approach 2:
The patent changes the physical-chemical parameter of the gate insulating layer by introducing phosphorus doping. This parameter change (adding phosphorus atoms to the gate insulating layer) alters the electrical characteristics at the interface, creating a potential barrier that suppresses hole current. The doping concentration and depth are carefully controlled to achieve optimal leakage current reduction while maintaining device performance.
2Reliability
If a phosphorus-doped layer is added to the gate insulating layer, then the off-current is reduced and image quality is improved, but the device structure becomes more complex
Solution Approach 1:
The patent applies preliminary action by forming the phosphorus-doped layer in the gate insulating layer before forming the active layer. This preliminary doping prepares the interface structure in advance, ensuring that when the active layer is formed, the phosphorus-doped region is already in position to suppress hole current. This sequencing integrates the complexity into an early fabrication step rather than requiring additional post-processing steps.
Solution Approach 2:
The patent creates a composite structure by combining the gate insulating layer material with phosphorus dopant atoms. This composite material approach results in a gate insulating layer with non-uniform composition - the bulk remains as the original insulating material while the interface region contains phosphorus-doped zones. This composite structure provides both the insulating properties and the hole-blocking functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a phosphorus-doped gate insulating layer significantly decreases off-current by about 63% compared to conventional designs, improving the electrical reliability and lifespan of thin film transistors, thus enhancing image quality and durability.
Implementation Method 1
the gate insulating layer includes a phosphorus-doped layer positioned adjacent to the active layer
Implementation Method 2
a behavior of electrons and a behavior of holes are not free because of characteristic of amorphous silicon, in which the Fermi level exists in the middle of an energy gap. Hence, a leakage current resulting from a hole current increases in an off-region
Data Source
AI summary
A thin film transistor array substrate having excellent characteristics and a method for manufacturing the same are disclosed. The thin film transistor array substrate includes a substrate, a gate electrode positioned on the substrate, a gate insulating layer positioned on the gate electrode, an active layer which is positioned on the gate insulating layer and includes a channel, an ohmic contact layer positioned on the active layer, and a source electrode and a drain electrode which are respectively connected to both sides of the active layer through the ohmic contact layer. The gate insulating layer includes a phosphorus-doped layer positioned adjacent to the active layer.