Phosphorus Implanted Poly-Silicon Sheet Resistance Reduction
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Solution Overview
Problem
Highly doped poly-silicon gate electrodes during high temperature anneals cause phosphorus penetration through gate oxide, leading to altered threshold voltage and degraded performance in semiconductor devices, particularly for short channel devices.
Innovation Solution
The process involves depositing intrinsic amorphous silicon at a specific temperature and implanting amorphizing species and phosphorus into the gate region, reducing phosphorus diffusion by using an Ar+ implant to adjust the poly-silicon sheet resistance and control phosphorus dosage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature anneal is used to achieve sufficient diffusion for driving the dope of the drain region underneath the poly-silicon gate edge, then the doping effectiveness is improved, but phosphorus penetrates through the gate oxide into the channel region altering threshold voltage and causing increased VT roll off
Solution Approach 1:
An oxygen plasma treatment layer is introduced as an intermediary between the phosphorus-doped poly-silicon gate and the gate oxide. This oxygen-rich layer acts as a diffusion barrier that prevents phosphorus from penetrating through the gate oxide into the channel region, while still allowing the high temperature anneal to achieve sufficient doping depth for the drain region.
Solution Approach 2:
The gate oxide is subjected to oxygen plasma treatment that changes its chemical composition and structure, creating an oxygen-enriched surface layer. This parameter change in the oxide layer's composition creates a phosphorus diffusion barrier, enabling high temperature annealing without phosphorus penetration into the channel.
2Reliability
If highly phosphorus-doped poly-silicon is used for gate electrode, then the gate conductivity is improved, but phosphorus diffusion through thermally grown oxide degrades device performance
Solution Approach 1:
The oxygen plasma-treated gate oxide surface acts as an intermediary barrier layer between the highly phosphorus-doped poly-silicon gate electrode and the underlying channel region. This intermediary layer allows the gate to maintain high conductivity through heavy phosphorus doping while preventing phosphorus diffusion into the channel that would degrade device performance.
Solution Approach 2:
Oxygen plasma treatment is performed on the gate oxide before the high temperature anneal and phosphorus diffusion process. This preliminary action creates an oxygen-enriched barrier layer in advance, which then prevents phosphorus diffusion during subsequent processing steps, allowing highly doped poly-silicon to be used without harmful diffusion effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes phosphorus penetration through the gate oxide, maintaining desired threshold voltage and reducing VT roll off for short channel devices, thereby enhancing device performance and yield while reducing manufacturing costs.
Implementation Method 1
depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region
Implementation Method 2
Amorphizing species are implanted at a first predetermined dose into the intrinsic amorphous silicon in the gate region
Implementation Method 3
phosphorus species are implanted into the gate region at a second predetermined dose
Implementation Method 4
phosphorus from the poly-silicon gate electrode diffuses through the gate oxide into the channel region of the transistor
Data Source
AI summary
There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.