Photo-detecting Circuit Reset Voltage for Flat Panel Detector

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In X-ray imaging with flat panel detectors, excessive irradiation leads to accumulated charges that cannot be completely discharged during the reset phase, causing interference and artifacts in captured images.

Innovation Solution

A photo-detecting circuit with a reset circuit that supplies a second voltage greater than the DC voltage, calculated as the difference between the DC voltage and the voltage at the second node, to accelerate the discharge of photo-generated charges, thereby improving image quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the reset phase uses standard discharge method, then the circuit structure remains simple, but the photo-generated charges cannot be completely discharged, causing interference and artifacts in captured images

Engineering Contradiction:
Improveimage qualityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The integrating circuit dynamically switches between two modes: integration mode for signal accumulation and reset mode for charge discharge. The circuit uses control signals to transition between these modes, enabling the same circuit to perform different functions at different times, thereby achieving complete charge discharge without adding permanent structural complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes the reference voltage parameter supplied to the integrating circuit during the reset phase. By adjusting this voltage parameter, the circuit creates a stronger discharge driving force that enables complete removal of photo-generated charges, improving image quality without requiring additional discharge components

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the reset phase extends longer to discharge charges, then more charges can be discharged, but the imaging speed decreases

Engineering Contradiction:
Improvecharge discharge completenessVSAvoidimaging speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The circuit prepares the integrating circuit for rapid discharge by pre-configuring the reset mode with an optimized reference voltage level before the discharge process begins. This preliminary preparation allows the discharge to proceed quickly and completely without extending the overall reset phase duration, maintaining high imaging speed

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures accurate reading of charges and enhances the quality of captured images by speeding up the reset process, reducing interference and artifacts.

Implementation Method 1

a photosensitive detector configured to accumulate photo-generated charges at a first node upon irradiation by light

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS11215716B2Photo-detecting circuit, driving method thereof and flat panel detector
Publication Date: 2022.01.04 BEIJING BOE OPTOELECTRONCIS TECH CO LTD
  • US11215716B2 patent drawing
  • US11215716B2 patent drawing
  • US11215716B2 patent drawing

AI summary

A photo-detecting circuit including a photosensitive detector configured to accumulate photo-generated charges at a first node upon irradiation by light, a transfer circuit configured to establish a current path to the first node in response to a first scan signal being active, an integrating circuit configured to selectively operate in a first mode in which the integrating circuit operates as an integrator to integrate a photocurrent and transfer an integration result to a second node for readout or a second mode in which the first input terminal of the integrating circuit is in conduction with the second node, and a reset circuit configured to selectively supply a first voltage or a second voltage to the second input terminal of the integrating circuit as a reference voltage. The second voltage is greater than the first voltage.