Photodetector Interface Circuit for Full-Frame Integration

The patent divides the integration process into discrete time segments using a digital counter that counts clock cycles during the integration period. Instead of using a single large capacitor to hold charge for the entire frame period, the system segments the integration into multiple clocked cycles, with each cycle contributing a quantized amount to the final digital value. This segmentation allows full-frame integration time without requiring impractically large capacitor sizes.

The patent replaces the traditional analog integration mechanism (relying on physical capacitor charge storage) with a digital counting mechanism. The transimpedance amplifier converts photodetector current to voltage, which then triggers comparator events that increment a digital counter. This substitution of mechanical/analog storage with digital counting enables precise measurement of integrated charge over full frame periods without being constrained by physical capacitor size limitations.

The patent merges multiple functions into a single integrated circuit unit cell: the transimpedance amplifier, comparator, digital counter, and control logic are all combined within each pixel's readout integrated circuit. This merging allows pixel-level digitization to be implemented without proportionally increasing overall system complexity, as the digitization components are shared and integrated efficiently at the pixel level rather than requiring separate complex subsystems.

The patent employs periodic clocking signals to control the digitization process. A clock signal periodically enables the comparator and counter operations, creating a regular rhythm of charge measurement and digitization. This periodic action simplifies the control logic compared to continuous operation, as the system only needs to manage discrete clock cycles rather than continuous analog processing, thereby reducing overall device complexity while achieving low noise equivalent bandwidth.

The patent maintains continuous integration action throughout the full frame period by using a clocked counting mechanism that accumulates digital values over every clock cycle. Rather than requiring the capacitor to hold charge for the entire integration duration (which would require large size), the system continuously accumulates quantized charge measurements in digital form across multiple clock cycles, maintaining integration capability without large capacitors.

The patent introduces a digital counter as an intermediary between the photodetector current and the final digital output. This counter mediates the integration process by accumulating clock cycle counts that represent integrated charge, replacing the need for large physical capacitors. The intermediary digital counting mechanism enables long integration times while keeping capacitor sizes practical, as the counter can accumulate values over arbitrary time periods without physical storage constraints.