Photodetector Pixel Structure for Uniform Active-Inactive Etching
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Solution Overview
Problem
The existing photodetection devices face challenges in manufacturing yield due to differential etching rates in active and inactive areas, leading to incomplete etching of semiconductor layers in inactive areas, which affects the efficiency and reliability of photodetection.
Innovation Solution
The photodetection device incorporates a structure where the second intrinsic semiconductor layer in inactive areas is etched at a lower rate, ensuring uniform etching and preventing incomplete etching, while the first intrinsic and extrinsic semiconductor layers in active areas are etched at higher rates, maintaining high manufacturing yield and photoelectric conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform etching rate is applied to both active and inactive areas, then manufacturing process is simplified, but incomplete etching occurs in inactive areas leading to yield decrease
Solution Approach 1:
The patent applies local quality by making the lower extrinsic semiconductor layer in inactive areas extend beyond the electrode layer perimeter, creating a local structural difference. This ensures that during etching, the inactive area layers are protected from incomplete etching while maintaining uniform etching conditions across the entire substrate, thus resolving the contradiction between manufacturing simplicity and etching completeness.
2Productivity
If etching rate is increased for active areas, then photoelectric conversion efficiency is improved, but incomplete etching occurs in surrounding inactive areas
Solution Approach 1:
The patent implements preliminary action by pre-configuring the lower extrinsic semiconductor layer in inactive areas to extend beyond the electrode layer before etching begins. This preliminary structural arrangement ensures that when high-rate etching is applied to active areas, the inactive area layers are already positioned to prevent etching penetration, thereby maintaining both high productivity and reliability.
3Manufacturing precision
If differential etching rates are applied to active and inactive areas, then etching completeness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimension (extension distance) of the lower extrinsic semiconductor layer in inactive areas rather than changing etching process parameters. This structural parameter change achieves differential etching protection without complicating the etching process control, thus improving etching completeness while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform etching of inactive area pixel units, preventing yield decreases and maintaining high photoelectric conversion efficiency by ensuring all pixel units are etched uniformly, thus enhancing the manufacturing process and device performance.
Implementation Method 1
a first intrinsic semiconductor layer on the first lower extrinsic semiconductor layer... a first upper extrinsic semiconductor layer containing a second extrinsic semiconductor and located on the first intrinsic semiconductor layer
Data Source
AI summary
A photodetection device includes a substrate and a plurality of pixel units. The plurality of pixel units includes a pixel unit including a first photodetector in an active area, and a pixel unit including a second photodetector in an inactive area. The first photodetector includes a first lower electrode layer, a first lower extrinsic semiconductor layer, a first intrinsic semiconductor layer, a first upper extrinsic semiconductor layer, and a first upper electrode layer. The second photodetector includes a second lower electrode layer, a second lower extrinsic semiconductor layer, a second intrinsic semiconductor layer, a second upper extrinsic semiconductor layer, and a second upper electrode layer. The second lower electrode layer is covered with the second lower extrinsic semiconductor layer and the second intrinsic semiconductor layer.