Avalanche Photodiode Counter Output Layout for Reduced Wiring Area
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Solution Overview
Problem
Existing signal processing devices face challenges in reducing the area required for wiring outputting digital signals, particularly in arranging wirings for outputting digital signals from a counter subsequent to the counter in information processing devices.
Innovation Solution
A signal processing device is designed with a plurality of pixel signal processing units arranged in both directions, where a signal line group is used to commonly output signals corresponding to multiple bits of digital signals from each pixel signal processing unit, reducing the number of pixel output signal lines and optimizing wiring efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate signal lines are used for each bit of digital signals from pixel signal processing units, then signal transmission reliability is improved, but wiring area increases
Solution Approach 1:
Multiple signal lines for different bits are merged into a single shared signal line. The patent combines multiple digital signal bits (D0-D3) that would traditionally require separate wiring into one common signal line, significantly reducing wiring area while maintaining signal integrity through coordinated control mechanisms.
Solution Approach 2:
The shared signal line serves multiple functions by transmitting different bit signals at different time intervals. The same physical wiring infrastructure is used to carry multiple pieces of information sequentially, making the wiring system multi-functional and reducing overall wiring requirements.
2Productivity
If the number of pixel output signal lines is reduced, then wiring efficiency is improved, but signal output delay increases
Solution Approach 1:
The system uses periodic time-division multiplexing where different bits are transmitted at different time intervals through the shared signal line. Each pixel signal processing unit outputs its digital signal bits sequentially (D0, then D1, then D2, then D3) in coordinated time slots, reducing wiring needs while managing output delay through structured timing.
Solution Approach 2:
The control signal generation unit pre-coordinates the output timing of each bit before transmission occurs. By establishing the transmission schedule in advance and synchronizing all pixel signal processing units, the system minimizes unexpected delays while using fewer signal lines.
3Area of stationary object
If signal lines are shared among multiple pixel signal processing units, then wiring area is reduced, but signal interference risk increases
Solution Approach 1:
Time-division multiplexing separates different signal transmissions into distinct time periods, preventing simultaneous signals from interfering with each other on the shared line. Each pixel unit transmits its bits in designated time slots, eliminating signal conflicts while sharing the same physical wiring.
Solution Approach 2:
The control signal generation unit coordinates transmission timing based on feedback about which pixel units are active and what data they need to transmit. This centralized control ensures that only one unit transmits at a time on the shared signal line, preventing interference while enabling efficient wiring utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the area required for wirings, enhances wiring efficiency, and minimizes the output delay by adjusting the resistance and capacitance between signal lines, while maintaining signal stability and accuracy.
Implementation Method 1
Each of the plurality of signal processing units acquires a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode
Data Source
AI summary
A signal processing device includes a plurality of pixel signal processing units and a signal line group. The plurality of pixel signal processing units is arranged in a first direction and a second direction, each of the plurality of signal processing units acquiring a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode. The signal line group is arranged corresponding to the plurality of pixel signal processing units arranged in the first direction and including a signal line to which a plurality of signals corresponding to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are commonly output.