Photoelectric Conversion Clock Trees for Compact Readout
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Solution Overview
Problem
Existing photoelectric conversion devices face challenges in miniaturization and power consumption due to increased circuit scale and clock buffer requirements for synchronization between readout and AD conversion controllers.
Innovation Solution
Implementing separate clock generators for drive and horizontal transfer units, with distinct clock trees to control the operation of the pixel array, horizontal transfer, and AD conversion, reducing the need for multiple clock buffers and minimizing circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock generator is used to control both the readout controller and AD conversion controller, then the circuit scale can be reduced, but it becomes difficult to maintain synchronization between the horizontal transfer operation and AD conversion operation
Solution Approach 1:
The clock generator is divided into two separate clock generators: a first clock generator for the readout controller and a second clock generator for the AD conversion controller. This segmentation allows independent control of each module while maintaining overall system synchronization through coordinated clock signal generation.
Solution Approach 2:
A clock buffer is introduced as an intermediary component between the two clock generators and the respective controllers. The clock buffer receives clock signals from both generators and distributes them to the readout controller and AD conversion controller, ensuring synchronized operation while allowing the generators to operate independently.
2Reliability
If multiple clock buffers are arranged for timing control to maintain synchronization, then the synchronization between readout and AD conversion controllers can be maintained, but the circuit scale and power consumption increase
Solution Approach 1:
The clock buffer is designed to serve multiple functions: it acts as a timing control element for synchronization, a signal distribution node for both controllers, and a phase adjustment mechanism. This multi-functionality reduces the need for multiple separate components while maintaining reliable synchronization.
3Reliability
If multiple clock buffers are arranged for timing control to maintain synchronization, then the synchronization between readout and AD conversion controllers can be maintained, but power consumption increases
Solution Approach 1:
The timing control function is extracted from multiple separate clock buffers and consolidated into a single multi-functional clock buffer. This extraction reduces the total number of active components involved in timing control, thereby reducing overall power consumption while maintaining synchronization reliability.
Data Source
AI summary
A photoelectric conversion device is provided. The device includes a pixel array in which pixels are arranged, a drive controller configured to drive the pixel array, a horizontal transfer unit configured to sequentially output analog signals respectively output from columns of the pixel array, an AD converter configured to convert an analog signal output from the horizontal transfer unit into a digital signal, a first clock generator configured to generate a clock signal used to control an operation of the drive controller, and a second clock generator configured to generate a clock signal used to control the horizontal transfer unit and the AD converter. A clock tree in which a clock signal is distributed from the first clock generator and a clock tree in which a clock signal is distributed from the second clock generator form clock trees different from each other.