Photoelectric Conversion Pixel Layout for Micro Loading Reduction
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Solution Overview
Problem
Photoelectric conversion devices with multiple pixels arranged in a matrix and dummy patterns outside the pixel region lead to increased frame area, resulting in larger device sizes and limitations on outer dimensions, necessitating a reduction in micro loading effects while maintaining device performance.
Innovation Solution
The implementation of a photoelectric conversion device structure that includes a first transistor, a first photoelectric conversion element, a second transistor acting as a dummy transistor, and an insulating layer with external terminals, where the second transistor is electrically floating and surrounds the active region, reducing micro loading effects without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy pattern is disposed outside the pixel region to reduce micro loading effect, then the micro loading effect is reduced, but the frame area and device size increase
Solution Approach 1:
The patent applies dimensionality change by moving the dummy transistor from a planar arrangement outside the pixel region to a vertical arrangement above the pixel region in a stacked configuration. This allows the dummy transistor to occupy the third dimension (vertical space) rather than expanding the two-dimensional frame area, thereby reducing micro loading effects without increasing the device's footprint.
Solution Approach 2:
The patent implements nesting by placing the dummy transistor within the vertical stack above the pixel region, effectively nesting multiple functional elements in the same spatial footprint. The dummy transistor is positioned above the pixel region with insulating layers separating them, allowing compact integration without increasing frame area.
2Area of stationary object
If the outer size is reduced with narrower frames, then the device size is reduced, but the ability to reduce micro loading effect is limited
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to place the dummy transistor above the pixel region. This stacked configuration enables effective micro loading reduction while maintaining a compact planar footprint with narrower frames, as the dummy structure occupies vertical space rather than horizontal space.
Solution Approach 2:
The patent applies local quality by positioning the dummy transistor specifically above the pixel region where micro loading effects need to be compensated. The insulating layers are selectively disposed between the pixel region and dummy transistor, providing localized micro loading reduction precisely where needed without requiring overall device enlargement.
3Manufacturing precision
If multiple dummy patterns are added to reduce micro loading effect, then the micro loading effect is reduced, but the device complexity increases
Solution Approach 1:
The patent merges the dummy transistor functionality with the existing pixel region structure by positioning it vertically above the pixel region. This integration approach combines multiple functions (pixel operation and micro loading compensation) into a single stacked structure, reducing overall device complexity compared to adding separate dummy patterns in the planar direction.
Solution Approach 2:
The patent reduces complexity by transitioning from a planar arrangement of multiple dummy patterns to a vertical stacked configuration. This dimensional change allows the dummy transistor to be integrated above the pixel region, simplifying the overall structure while maintaining micro loading reduction effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses micro loading effects, maintains device performance, and allows for narrower frames without increasing the overall size of the photoelectric conversion device, enhancing its operational efficiency and image generation capabilities.
Implementation Method 1
a first photoelectric conversion element that is disposed on the first region of the substrate and is electrically connected to the first transistor
Data Source
AI summary
A photoelectric conversion device according to one embodiment includes a first transistor and a first photoelectric conversion element disposed on a first region, a second transistor disposed on a second region, an insulating layer that covers the first transistor, the first photoelectric conversion element, and the second transistor, and a first terminal that is disposed on the insulating layer, is electrically connected to one of the first transistor and the first photoelectric conversion element, and is connectable to an outside. The second transistor is a dummy transistor of the first transistor.