Photoelectric conversion apparatus, photoelectric conversion system, moving body, and semiconductor substrate
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Solution Overview
Problem
The increasing power consumption in photoelectric conversion apparatuses due to high-speed digital addition processing of binary data from multiple pixel samples is a significant issue, as it affects the efficiency and performance of these devices.
Innovation Solution
The apparatus employs a comparator to convert pixel output signals into digital signals and uses a serial binary adder with a 1-bit adder for subtraction processing, reducing circuit scale and power consumption while maintaining high-speed addition and subtraction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital addition processing is performed at high speed to add multiple binary data pieces, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent divides the digital addition processing into two stages: first, the comparator performs parallel binary comparison of multiple pixel data pieces against a reference signal to generate comparison results; second, a sequential adder sequentially adds these comparison results. This segmentation avoids the high power consumption of fully parallel high-speed addition while maintaining acceptable processing speed through the efficient sequential stage.
Solution Approach 2:
The patent replaces the traditional mechanical/electrical parallel adder system with a comparator-based system that performs binary comparison. The comparator generates digital signals through optical/electrical field comparison rather than direct electrical addition, reducing power consumption while achieving the same functional goal of converting multiple binary data pieces into a final digital value.
2Productivity
If parallel addition processing is used to add multiple binary data pieces, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the addition function into a comparator that handles parallel comparison operations and a sequential adder that handles the final summation. This division allows the system to achieve parallel processing benefits in the comparison stage while using a simpler sequential adder, reducing overall circuit complexity compared to a fully parallel adder system.
Solution Approach 2:
The comparator serves multiple functions: it compares pixel data against the reference signal, generates digital comparison results, and prepares data for the sequential adder. This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby reducing overall device complexity while maintaining processing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and improves image quality by minimizing noise and circuit size, while also shortening the processing cycle for each frame, thus enhancing the overall performance of the photoelectric conversion apparatus.
Implementation Method 1
Each of the plurality of pixels includes a photoelectric conversion element that converts incident light into a signal
Data Source
AI summary
An apparatus includes a plurality of pixels, a comparator configured to compare an output signal of each of the plurality of pixels with a reference signal, and a counter of K bits (K is a natural number) configured to operate in parallel with operation of the comparator. The apparatus converts the output signal of each of the plurality of pixels into a digital signal using an output of the comparator and an output of the counter. The apparatus includes an addition unit configured to add a plurality of the digital signals. The addition unit includes a serial binary adder of M bits (M is a natural number less than K).