Photoimageable Dielectric Layer for Semiconductor Package Fabrication
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Solution Overview
Problem
Molded Interconnection System Ball Grid Array (MIS-BGA) architectures face limitations in supporting multiple layers and high z-heights, requiring expensive grinding steps and being largely confined to panel-based manufacturing processes due to constraints related to copper pillar heights and availability of thin mold film materials.
Innovation Solution
The use of a photoimagable dielectric (PID) layer with mechanical properties similar to mold materials, allowing for reduced need for dry resist film lamination steps and elimination of grinding processes, enabling multiple layer counts and integration of components like capacitors and inductors, while facilitating redistribution layers and fan-out packaging on both wafers and panels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MIS-BGA architectures use traditional mold materials and processes, then manufacturing is simplified, but layer count is limited and z-height constraints require expensive grinding steps
Solution Approach 1:
The patent changes the material parameter from traditional mold materials to photoimageable dielectric materials, which have different mechanical and processing properties. This enables precise control of layer count and z-height through photolithographic patterning without requiring mechanical grinding steps, thereby improving manufacturing precision while managing device complexity
Solution Approach 2:
The patent replaces mechanical grinding processes with photolithographic patterning processes. Instead of using mechanical means to control z-height and layer dimensions, the invention uses light-based patterning to achieve precise dimensional control, eliminating expensive grinding steps and reducing process complexity
2Manufacturing precision
If thin mold film materials are used to enable multiple layers, then layer count increases, but material availability is limited and costs increase
Solution Approach 1:
The photoimageable dielectric material serves multiple functions: it acts as both the dielectric layer and the mold material, eliminating the need for separate thin mold film materials. This multi-functionality enables increased layer count while using readily available, cost-effective photoimageable materials instead of specialized thin mold films
3Manufacturing precision
If copper pillar heights are increased to support more layers, then layer count increases, but manufacturing constraints and costs increase
Solution Approach 1:
The patent shifts the approach from increasing vertical dimension (copper pillar height) to using photolithographic patterning in the horizontal plane to define layer structures. This dimensional shift allows multiple layers to be formed with standard-height copper pillars by using light-based patterning to create precise layer boundaries and features, reducing manufacturing constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing costs, enhances cavity depth flexibility, improves fine line and space capabilities, and allows for better scaling and integration of components within semiconductor packages, expanding applications beyond panel-based manufacturing.
Implementation Method 1
The PID layer can be exposed and developed to form the cavities and the redistribution layers
Data Source
AI summary
Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.