Photolithography Alignment Mark Layout for Lower Overlay Error
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Solution Overview
Problem
Existing photolithography techniques face challenges in accurately aligning and printing layers of semiconductor ICs due to insufficient overlay raw data from a low number of alignment marks, leading to increased overlay errors and poor performance in semiconductor manufacturing.
Innovation Solution
Implementing a high density of alignment marks distributed in wafer scribe lines and within individual chips, with specific patterns and duty ratios, to increase overlay raw data and improve positional accuracy of photolithography tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a low number of alignment marks are used in photolithography, then the device complexity is reduced, but the measurement precision of overlay position deteriorates
Solution Approach 1:
The patent divides the alignment mark system into multiple segments distributed across scribe lines and chip regions. Instead of using a single alignment mark, multiple alignment marks are placed at different locations (scribe lines between chips and within chip regions), segmenting the measurement function across multiple points to improve overall overlay accuracy while maintaining manageable complexity
Solution Approach 2:
The patent extends the alignment mark distribution from a single dimension to multiple dimensions by placing alignment marks both in scribe lines (between chips) and within individual chip regions. This multi-dimensional distribution increases the density and coverage of alignment marks, improving measurement precision without proportionally increasing device complexity
2Ease of manufacture
If a low number of alignment marks are used, then the manufacturing process is simpler, but the manufacturing precision of layer alignment deteriorates
Solution Approach 1:
The alignment mark structure is segmented into multiple discrete marks distributed across scribe lines and chip regions. This segmentation allows each individual alignment mark to be manufactured using standard processes while the collective arrangement achieves high precision layer alignment that would be difficult with fewer, more complex marks
Solution Approach 2:
The patent changes the parameter of alignment mark density from low to high by distributing multiple alignment marks across scribe lines and chip regions. This parameter change improves manufacturing precision for layer alignment while the alignment marks themselves are formed using existing photolithography processes, maintaining ease of manufacture
3Loss of time
If overlay raw data is insufficient, then the measurement process is faster, but the reliability of positional adjustment deteriorates
Solution Approach 1:
Alignment marks are formed in advance during the photolithography process on the substrate before final layer patterning. This preliminary action ensures that overlay raw data is collected early from multiple distributed marks, providing sufficient and reliable data for positional adjustment calculations without delaying subsequent manufacturing steps
Solution Approach 2:
The patent implements a feedback mechanism where overlay raw data collected from multiple alignment marks is used to determine offset distances, which then inform positional adjustments of the photolithography tool. This feedback loop ensures reliable positional adjustment by continuously using measured data from the distributed alignment mark network to correct alignment errors
Data Source
AI summary
A semiconductor device includes a substrate having a plurality of chip regions. In some embodiments, the semiconductor device further includes a plurality of scribe lines interposing the plurality of chip regions. In some examples, the semiconductor device further includes a first plurality of alignment mark regions distributed within the plurality of scribe lines. In some embodiments, the semiconductor device further includes a second plurality of alignment mark regions distributed within each of the plurality of chip regions.