Photolithography Alignment Marks for Semiconductor Overlay Accuracy
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in achieving high overlay accuracy, particularly in regions far from alignment marks due to magnification errors, distortion, and substrate expansion/contraction, leading to increased complexity and steps in the process.
Innovation Solution
A method involving a first photolithography step for forming a device pattern and alignment marks across an entire device region using a single mask, followed by a second step where each divided region is exposed using separate masks with alignment marks at corner portions, allowing precise alignment and reducing the number of steps required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If one-shot exposure is used to form a layer, then the manufacturing process is simplified, but high overlay accuracy cannot be obtained in regions far from alignment marks due to magnification error and distortion
Solution Approach 1:
The patent divides the exposure process into two segments: first, one-shot exposure forms the base layer with alignment marks; second, divided exposure forms subsequent layers using multiple exposure steps. Each divided exposure region uses alignment marks within that region for precise alignment, combining the simplicity of one-shot exposure with the precision of divided exposure where needed.
2Manufacturing precision
If divided exposure is performed multiple times with alignment marks formed by one-shot exposure, then overlay accuracy improves, but the number of manufacturing steps increases
Solution Approach 1:
The patent merges the formation of alignment marks with the formation of circuit patterns in the first photolithography step. By including alignment mark patterns in the first mask along with circuit patterns, both are formed simultaneously in one exposure step, eliminating the need for a separate photolithography step dedicated only to alignment marks.
Solution Approach 2:
The first mask serves multiple functions: it forms both the circuit patterns of the first layer and the alignment marks that will be used for subsequent divided exposure steps. This multi-functional approach reduces the total number of masks and photolithography steps required.
3Area of stationary object
If alignment marks are formed far from the center of the substrate, then coverage is improved, but magnification error and distortion increase
Solution Approach 1:
The patent places multiple alignment marks at different locations across the substrate, including corner regions. Each divided exposure region uses its own local alignment marks for alignment, allowing precise overlay control in each local region while maintaining broad coverage across the entire substrate area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of large-area semiconductor devices with high overlay accuracy while minimizing the number of process steps, improving precision and reducing errors such as magnification and distortion issues.
Implementation Method 1
a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks
Implementation Method 2
a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto
Data Source
AI summary
A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.