Photolithography Process Selection for Layout-Specific Feature Precision
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Solution Overview
Problem
The challenge in increasing computing power in integrated circuits lies in the limitations of current photolithography processes to form very small features and interconnection structures, which affect the density of transistors on semiconductor wafers.
Innovation Solution
A semiconductor process system that selects among different types of photolithography processes, such as EUV and 193i, based on layout analysis to optimize feature formation, using a layout analyzer to determine the most suitable process for each layout, thereby managing photolithography resources effectively and improving wafer yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional photolithography processes are used to form smaller features, then feature size is reduced, but manufacturing precision deteriorates due to process limitations
Solution Approach 1:
The patent segments the wafer into different layout regions and applies different photolithography processes to different regions. The layout analyzer identifies specific regions requiring EUV processing based on feature density and size criteria, while other regions use conventional 193i processes. This segmentation allows small critical features to receive specialized processing while maintaining productivity for less critical areas.
Solution Approach 2:
The patent applies local quality by tailoring the photolithography process to specific layout regions. Instead of using a uniform process across the entire wafer, the system analyzes layout characteristics and assigns EUV processing selectively to regions with features below a predetermined size threshold or high density requirements, while using conventional processes for other regions. This ensures optimal precision where needed without compromising overall productivity.
2Manufacturing precision
If EUV photolithography process is used for all layouts, then manufacturing precision is improved, but device complexity and resource management become more challenging
Solution Approach 1:
The patent implements preliminary action by performing layout analysis before photolithography processing. The layout analyzer examines the semiconductor layout data in advance, identifies regions requiring EUV processing based on feature size and density criteria, and generates a process selection map. This preliminary classification simplifies subsequent process execution by pre-determining which regions need specialized EUV treatment versus conventional processing.
Solution Approach 2:
The layout analyzer serves as an intermediary between the layout design and photolithography processing systems. It analyzes layout characteristics, applies selection rules to determine appropriate processes, and translates design requirements into process selection decisions. This intermediary layer automates the complex decision-making process, reducing manual intervention while optimizing process selection based on layout-specific requirements.
3Manufacturing precision
If multiple photolithography processes are used for different layouts, then manufacturing precision is improved, but productivity decreases due to process variability
Solution Approach 1:
The patent segments the wafer processing into different process zones based on layout analysis. By identifying and isolating only the specific regions requiring EUV processing, the system minimizes the impact of process variability on overall productivity. Conventional 193i processes continue for the majority of regions, maintaining high throughput, while EUV processing is applied selectively to critical regions, achieving precision without sacrificing overall wafer throughput.
4Quantity of substance
If feature size is reduced to increase transistor density, then computing power increases, but photolithography process capability becomes insufficient
Solution Approach 1:
The patent applies local quality by matching process capability to feature requirements. The layout analyzer identifies regions with features below the capability threshold of conventional 193i processes and assigns EUV processing to those specific regions. This allows the system to achieve the necessary manufacturing precision for sub-10nm features where required, enabling continued transistor density increases, while using conventional processes for larger features to maintain productivity.
Data Source
AI summary
A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.