Multi-Patterning Photomask Stitching for IC Fabrication

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Solution Overview

Problem

Conventional multi-patterning processes for fabricating integrated circuits require a large number of photomasks, increasing costs and reducing process efficiency due to the need for separate masks for metal lines and interconnecting vias/contacts.

Innovation Solution

Decomposing the master pattern layout into sub-patterns that include overlapping line feature patterns for both metal lines and interconnecting vias/contacts, allowing for the generation of fewer photomasks by integrating the details of both into each sub-pattern, thereby reducing the total number of masks required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional multi-patterning processes use separate photomasks for metal lines and interconnecting vias/contacts, then manufacturing precision is maintained, but the number of photomasks increases leading to higher costs and reduced process efficiency

Engineering Contradiction:
Improvepattern resolutionVSAvoidnumber of photomasks
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the patterning of metal lines and interconnecting vias/contacts into a single photomask by using overlapping line feature patterns. The first and second line feature patterns from different sub-patterns overlap to define the stitch location for interconnecting vias/contacts, eliminating the need for separate photomasks for these features.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each photomask in the invention serves multiple functions by containing both metal line patterns and interconnecting via/contact patterns. The same photomask is used to define both the metal line geometry and the locations of interconnecting structures through the overlapping pattern approach.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If conventional multi-patterning processes decompose master pattern layout into separate sub-patterns for metal lines and vias/contacts, then manufacturing precision is maintained, but process efficiency decreases due to increased number of photomasks

Engineering Contradiction:
Improvepattern decomposition accuracyVSAvoidprocess efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The invention merges the decomposition of metal line patterns and via/contact patterns into unified sub-patterns. Each sub-pattern contains both metal line features and interconnecting structure features that overlap to define stitch locations, reducing the total number of photomasks required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The overlapping line feature patterns are designed in advance during mask generation to pre-defines the stitch locations for interconnecting vias/contacts. This preliminary integration of via/contact definition into the line pattern decomposition eliminates subsequent separate patterning steps.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If separate photomasks are used for metal lines and interconnecting vias/contacts, then pattern fidelity is maintained, but cost efficiency decreases due to increased mask quantity

Engineering Contradiction:
Improvepattern fidelityVSAvoidcost efficiency
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the definition of metal lines and interconnecting vias/contacts into single photomasks through overlapping line feature patterns. This consolidation maintains pattern fidelity while reducing the total number of photomasks, thereby improving cost efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9530689B2Methods for fabricating integrated circuits using multi-patterning processes
Publication Date: 2016.12.27 GLOBALFOUNDRIES US INC
  • US9530689B2 patent drawing
  • US9530689B2 patent drawing
  • US9530689B2 patent drawing

AI summary

Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.