Photon Detector Array Assembly With 3D Interconnect Tiling
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Solution Overview
Problem
Existing photon detector arrays face challenges in creating large arrays with uniform pixel spacing and high resolution due to issues with signal flow and capacitance in interconnects, making it difficult to tile individual arrays edge-to-edge without gaps and maintaining uniform pixel pitch.
Innovation Solution
The use of die carriers with conductor layers and 3D connections between photon detector arrays and ROIC semiconductor dies, employing semiconductor manufacturing technology to reduce lead-to-lead capacitance and enable uniform pitch across larger arrays, allowing for edge-to-edge tiling with minimal spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If individual detector arrays are joined together at the edges to form large arrays, then the array size increases to image large objects, but unwanted intervening spaces appear between arrays disrupting uniform pixel spacing
Solution Approach 1:
The patent merges multiple detector arrays into a single monolithic photon detector array structure, eliminating the need to join separate arrays at their edges. This integration removes intervening spaces and ensures uniform pixel spacing across the entire large array, while maintaining the increased area needed for imaging large objects.
Solution Approach 2:
The patent transitions from a planar 2D arrangement of separate detector arrays to a three-dimensional stacked architecture where multiple detector arrays are vertically integrated. This dimensional change allows edge-to-edge coupling without horizontal gaps, achieving uniform pixel spacing while maintaining large effective detection area.
2Manufacturing precision
If three-dimensional signal flow is used to enable edge-to-edge coupling of detector arrays, then uniform pixel spacing is achieved, but lead-to-lead capacitance increases causing signal interference
Solution Approach 1:
The patent utilizes three-dimensional stacking to route signals vertically through separate conductor layers rather than horizontally through dense interconnects. This vertical signal flow in the third dimension reduces lead-to-lead capacitance and minimizes signal interference while maintaining uniform pixel spacing across the large detector array.
Solution Approach 2:
The patent introduces intermediate conductor layers and interposer structures that mediate between detector pixels and readout circuits. These intermediate structures provide optimized signal pathways that reduce capacitance and signal interference while enabling the three-dimensional architecture required for uniform pixel spacing.
3Measurement precision
If smaller pixel size is used to achieve higher resolution, then image resolution improves, but the number of pixels per array increases requiring more complex interconnects
Solution Approach 1:
The patent employs three-dimensional stacking with multiple conductor layers to handle the increased number of pixels required for high resolution. By routing signals vertically through stacked layers rather than through dense planar interconnects, the system manages the complexity of high-resolution imaging without proportionally increasing interconnect complexity.
Solution Approach 2:
The patent segments the detector array into multiple stacked layers, each with its own conductor layer. This segmentation allows independent optimization of each layer's interconnect structure, reducing overall complexity while supporting the high pixel count needed for high resolution imaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of large photon detector arrays with uniform pixel pitch and reduced signal interference, improving performance and reducing costs by integrating signal processing components directly into the detector assembly.
Implementation Method 1
a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die
Implementation Method 2
Each pixel in the photon detector array captures photons and converts them into an electrical signal
Data Source
AI summary
In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.