Single Photon Counting Pixel Detector Chip With Negligible Dead Time

The patent implements a multi-layer transistor architecture where transistors are stacked vertically across multiple layers (first layer, second layer, third layer) rather than being confined to a single planar layer. This vertical stacking enables significantly more transistors to be integrated within the same pixel footprint, thereby maintaining image resolution while increasing functional complexity.

The patent employs nested transistor structures where transistors in upper layers are positioned directly above or adjacent to transistors in lower layers, creating a three-dimensional integrated structure. This nesting approach maximizes the use of available space within each pixel, allowing complex functionality to be achieved without increasing pixel area.

The patent implements a dual-buffer architecture where pixel data is pre-loaded into a first buffer during one readout cycle while simultaneously being read out from a second buffer. This overlapping of data loading and readout operations eliminates idle time between frames, effectively reducing the dead time and enabling higher frame rates.

The patent maintains continuous data flow through the pipeline by implementing overlapping readout and load operations. While data is being read out from one buffer, the next frame's data is being loaded into the other buffer, ensuring that the readout circuitry is never idle and the useful action continues without interruption across multiple frames.