Photon Counting Readout Chip Parallel Multiplexing
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Solution Overview
Problem
Existing single photon-counting imaging devices face limitations in data readout speed without compromising accuracy, particularly in high flux synchrotron radiation applications where rapid data processing is crucial for time-resolved diffraction experiments.
Innovation Solution
A readout chip with binary counters of variable length and parallel data output capabilities, allowing selective multiplexing of data outputs and control signals to optimize readout speed, along with programmable bits for fine-tuning and channel control, enables faster data retrieval by reading out only necessary bits and simplifying control signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a pseudo-random counter (shift register with XOR feedback) is used for photon counting, then the counter can handle high counting rates, but the readout time increases significantly (at least 1+18+1 cycles for an 18 bit register)
Solution Approach 1:
The patent divides the counter into multiple independent binary counters, each handling a specific bit position. Instead of using a single pseudo-random counter that processes all bits sequentially, the invention segments the counting function across multiple parallel binary counters, allowing simultaneous readout of multiple bits and significantly reducing total readout time.
Solution Approach 2:
The patent transitions from a one-dimensional sequential readout approach (reading bits one after another in a single sequence) to a multi-dimensional parallel readout structure. Multiple binary counters operate independently and can be read out in parallel, effectively adding a temporal dimension to the readout process and reducing the number of cycles required.
2Loss of information
If all bits of a counter are read out sequentially, then complete counting data is obtained, but the readout speed decreases for channels with low counting rates
Solution Approach 1:
The patent implements variable length readout where only the necessary number of bits are read out for each channel based on its counting rate. For channels with low counting rates, fewer bits need to be read out since the count value will be small. This partial readout approach maintains data completeness for the required precision while significantly improving readout speed for low-activity channels.
Solution Approach 2:
The patent introduces dynamic adaptability in the readout process by making the readout length variable rather than fixed. The system can adjust the number of bits read out based on the actual counting requirements of each channel, optimizing the balance between data completeness and readout speed for different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces readout time by up to 50% for channels with lower counting rates, enhancing the speed and efficiency of data acquisition in photon-counting applications without sacrificing accuracy, particularly beneficial for time-resolved crystallographic and diffraction analyses.
Implementation Method 1
a layer of photosensitive material; an NxM array of photodetector diodes arranged in said layer of photosensitive material
Data Source
Figure 1
AI summary
It is the aim of the present invention to improve the properties and the speed of readout electronic significantly without losing accuracy of the counting in photon-counting imaging devices. This aim is achieved according to the present invention by a readout chip (2) for single photon counting, comprising: a) a plurality of N individually working channels each assigned to a respective detector diode; each channel comprising a counter (81 to 8128) being designed as a binary counter having a length of M bits and a number of programmable bits (pbl to pbl28); b) a serial or parallel data input shift register (4) for entering values for the counter (81 to 8128) and the programmable bits (pbl to pbl28); and c) a number of data output shift register (16); each having a number of K data outputs (20), whereby means (18) are provided for selectively multiplexing each of the K data outputs (20) onto a selectable bit of the data output shift register (16). These features allow a much faster readout of the counter since the counter can be readout in parallel groups of K bits each cycle. Further, a variable length of selectable bits for each counter in each channel can be readout advantageously by multiplexing the K data outputs to the bits of interest which increases the speed of readout tremendeously.