Photonic Chip Access Trench for Debris-Free Grating Coupling
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Solution Overview
Problem
Existing methods for removing semiconductor integrated circuit materials in photonic integrated circuits result in debris and non-uniform dicing depths, leading to optical signal loss and damage to grating couplers, which degrade optical coupling efficiency and yield.
Innovation Solution
A multi-step dry etching process is employed to etch trenches in selected regions of the EIC/PIC die stack, using Bosch etching and low selectivity etching to remove EIC materials, followed by oxide deposition on sidewalls to form passivation liners, ensuring precise and debris-free material removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dicing or laser drilling is used to remove EIC materials, then material removal is achieved, but debris is generated and dicing depths are non-uniform
Solution Approach 1:
The patent replaces mechanical dicing and laser drilling methods with a plasma-based etching process. The plasma etching uses reactive ions to chemically etch away semiconductor materials, eliminating mechanical contact and laser-induced debris generation while achieving uniform and precise material removal through controlled plasma parameters.
Solution Approach 2:
The patent employs multiple etching steps with different plasma parameters (gas composition, power, pressure) to achieve selective removal of EIC materials. By changing etching parameters between steps, the process achieves precise control over material removal depth and selectivity, ensuring complete removal without debris while protecting underlying structures.
2Manufacturing precision
If conventional etching is used to remove EIC materials, then material removal is achieved, but optical signal loss occurs
Solution Approach 1:
The patent replaces mechanical and laser-based removal methods with plasma etching, which chemically removes materials without generating debris that would scatter or absorb optical signals. The clean sidewalls and smooth surfaces produced by plasma etching minimize optical interference while achieving precise material removal.
Solution Approach 2:
The patent uses multiple etching steps with optimized plasma parameters to achieve precise material removal depth. By controlling etching parameters, the process removes only the necessary EIC materials while preserving the integrity of underlying grating couplers and optical structures, preventing optical signal loss.
3Productivity
If conventional removal methods are used, then EIC materials are removed, but grating couplers are damaged
Solution Approach 1:
The patent divides the material removal process into multiple sequential etching steps, each targeting specific materials or regions. This segmentation allows selective removal of EIC materials while preserving grating coupler structures through controlled etching depths and chemistries in each step.
Solution Approach 2:
The patent employs different plasma etching parameters for different etching steps, with each step optimized for specific material removal while protecting underlying structures. By changing gas composition, power levels, and exposure times between steps, the process achieves efficient EIC material removal while maintaining grating coupler integrity.
4Adaptability or versatility
If wafer-to-wafer bonding is used to integrate PIC and EIC, then system integration is achieved, but optical access to grating couplers is blocked
Solution Approach 1:
The patent segments the wafer stack into distinct regions for bonding and optical access. By creating localized openings through the bonded wafer stack using plasma etching, the process maintains the integrated structure while providing access pathways for optical signals to reach grating couplers in the PIC wafer.
Solution Approach 2:
The patent addresses the optical access problem by creating vertical pathways through the bonded wafer stack using plasma etching. This three-dimensional approach allows optical signals to access grating couplers from the bonded side, effectively solving the blocking issue while preserving the wafer-to-wafer integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves optical coupling efficiency and yield by achieving precise and complete removal of semiconductor materials, reducing optical signal loss and maintaining grating coupler integrity.
Implementation Method 1
etching a region of the semiconductor substrate under the first opening using the first patterned etch mask layer in a second etching process
Implementation Method 2
oxide deposition on sidewalls to form passivation liners
Data Source
AI summary
A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.