Wafer-Scale Photonic Chip Qualification Using Grating Couplers

Solution Overview

Problem

The high cost and risk of damaging photonic chips during individual testing after dicing, as well as the need for additional packaging before evaluation, necessitate a method for qualifying photonic chips on uncut wafers before separation.

Innovation Solution

A qualification apparatus and method featuring a wafer with a photonic chip and a test port incorporating a grating coupler that interacts with optical radiation at an angle, allowing for pre-dicing testing without damaging the chips, and optionally removing the grating coupler post-test.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If photonic chips are diced into separate chips before testing, then individual chip testing can be performed, but the risk of damaging chips during manipulation increases and additional packaging is required

Engineering Contradiction:

Improveindividual chip testing capabilityVSAvoidchip damage risk

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent performs testing on the wafer before dicing the photonic chips into individual chips. The test ports are fabricated and functional testing is conducted while the chips remain on the wafer substrate, allowing qualification to occur prior to the potentially damaging dicing and packaging operations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces test ports with grating couplers as intermediary structures that enable optical access to the photonic circuits on the wafer. These test ports serve as mediators that allow testing equipment to interface with the chips without requiring the chips to be physically manipulated or packaged first

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If photonic chips are tested individually after dicing, then each chip can be evaluated, but the manufacturing cost increases due to packaging requirements

Engineering Contradiction:

Improveindividual chip evaluation accuracyVSAvoidmanufacturing cost

Core Design Contradiction:

Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent performs testing on the wafer before dicing the photonic chips into individual chips. The test ports are fabricated and functional testing is conducted while the chips remain on the wafer substrate, allowing qualification to occur prior to the potentially damaging dicing and packaging operations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent combines multiple test ports onto a single wafer substrate, allowing parallel testing of multiple photonic chips simultaneously. This merging of testing capabilities reduces the overall manufacturing cost by eliminating individual packaging and handling requirements for each chip

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If test ports are added to the wafer, then pre-dicing testing can be performed, but the device complexity increases

Engineering Contradiction:

Improvepre-dicing qualification capabilityVSAvoidwafer structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the wafer into multiple regions, each containing photonic chips and associated test ports. The test ports are spatially separated from the main photonic circuits but remain optically coupled through waveguides, allowing independent testing without interfering with the primary device functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces test ports with grating couplers as intermediary structures that enable optical access to the photonic circuits on the wafer. These test ports serve as mediators that allow testing equipment to interface with the chips without requiring the chips to be physically manipulated or packaged first

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables cost-effective, wafer-scale qualification of photonic chips, reducing damage risk and allowing for efficient identification and separation of defective chips while maintaining minimal optical path disruption.

Implementation Method 1

a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer

Methodology Applied

Scientific EffectGrating coupler diffraction: Diffraction Grating

Data Source

PatentUS10359567B2Test systems and methods for chips in wafer scale photonic systems

Publication Date: 2019.07.23 NOKIA SOLUTIONS & NETWORKS OY

AI summary

A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate.