Photonic I/O Chiplet and Gearbox Layout for Low-Power Ethernet Switching
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Solution Overview
Problem
Existing optical data communication systems face challenges in achieving reliable and efficient modulation and reception of optical signals, requiring improved devices for efficient signal conversion and transmission.
Innovation Solution
The implementation of a photonic chip pod comprising a substrate, a photonic input/output chiplet, and a gearbox chiplet, which includes a parallel electrical interface, a photonic interface, and optical macros for efficient signal conversion between electrical and optical domains, along with a gearbox chiplet for interfacing with other chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional optical communication devices are used, then reliable optical signal modulation and reception is achieved, but power consumption is high and energy efficiency is poor
Solution Approach 1:
The patent divides the optical communication system into separate functional modules: photonic I/O chiplets for optical signal processing and gearbox chiplets for electrical signal conversion. This segmentation allows each module to be optimized independently, with the photonic chiplet focusing on low-power optical modulation and detection while the gearbox handles electrical interfacing, thereby reducing overall power consumption without compromising signal reliability
Solution Approach 2:
The gearbox chiplet serves as an intermediary between the photonic I/O chiplet and the CMOS switch chip, converting parallel electrical signals to serial signals and vice versa. This intermediary component enables efficient interfacing between different signal domains and protocols, maintaining transmission reliability while allowing the photonic chiplet to operate at optimal low power levels
2Productivity
If data transfer rate is increased to 100 Tbps, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional electrical signal transmission with optical signal transmission for high-speed data paths. By using photonic I/O chiplets with integrated optical modulators and detectors, the system achieves 100 Tbps data transfer rates with lower power consumption compared to electrical interconnects, as optical signals experience less attenuation and interference at high frequencies
Solution Approach 2:
The patent merges multiple functions into integrated photonic I/O chiplets that combine optical modulators, detectors, and signal processing circuits in a single package. This integration reduces the number of discrete components and interconnections, thereby reducing overall power consumption while maintaining 100 Tbps bandwidth capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed data transfer rates of up to 100 Tbps with reduced power consumption and improved energy efficiency, facilitating seamless integration into CMOS chip packaging ecosystems.
Implementation Method 1
a plurality of optical macros implemented between the photonic interface and the parallel electrical interface
Data Source
AI summary
A network switch system-in-package includes a carrier substrate with a network switch chip and a plurality of photonic input/output modules disposed on the carrier substrate. Each of the plurality of photonic input/output modules includes a module substrate and a plurality of photonic chip pods disposed on the module substrate. Each photonic chip pod includes a pod substrate with a photonic input/output chiplet and a gearbox chiplet attached to the pod substrate. The photonic input/output chiplet includes a parallel electrical interface, a photonic interface, and a plurality of optical macros implemented between the photonic interface and the parallel electrical interface. The gearbox chiplet electrically connects with the parallel electrical interface of the photonic input/output chiplet and a serial electrical interface of the network switch chip. The gearbox chiplet converts between the parallel electrical interface of the photonic input/output chiplet and the serial electrical interface of the network switch chip.