Photonic Circuit Layout Verification for Curvilinear Shapes
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Solution Overview
Problem
Conventional physical verification tools, such as design rule checking (DRC) and layout-versus-schematic (LVS), are inadequate for processing curvilinear shapes in silicon photonics, which are essential for advanced photonic devices due to their energy efficiency and data transmission speed advantages over electronic computing.
Innovation Solution
A method involving the extraction of a preliminary netlist from a circuit design, identification of geometric patterns for photonic devices, generation of a new layout design based on these patterns, and comparison with the original layout to verify connectivity and geometric elements, using a layout versus schematic tool that treats photonic devices as black boxes and accounts for rotation and location information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional physical verification tools (DRC and LVS) are used for photonic devices, then the verification process is simple and fast, but the tools cannot properly process curvilinear shapes which are essential for photonic devices
Solution Approach 1:
The patent introduces an intermediary representation system that converts curvilinear geometric patterns into discrete topological features (nodes, edges, regions) that can be processed by conventional verification tools. This intermediary topological model acts as a bridge between the curvilinear design and the Manhattan-shaped tool expectations, enabling accurate verification without requiring complete tool redesign.
Solution Approach 2:
The patent transforms the verification approach by changing the parameter representation from continuous curvilinear geometry to discrete topological parameters (connectivity, adjacency, enclosure relationships). This parameter transformation allows conventional tools to handle curvilinear shapes by operating on the topological properties rather than the geometric details.
2Use of energy by moving object
If curvilinear patterns are used in silicon photonics, then energy efficiency and data transmission speed improve, but conventional verification tools cannot detect and validate these patterns
Solution Approach 1:
The patent replaces the mechanical geometric processing approach of conventional tools with a topological analysis approach. Instead of relying on geometric shape matching and coordinate-based verification, the system uses topological relationships (connectivity, adjacency, enclosure) to validate curvilinear patterns, enabling reliable verification of energy-efficient photonic designs.
Solution Approach 2:
The patent performs preliminary extraction of topological features from curvilinear geometric patterns before verification. By pre-processing the curvilinear designs into topological representations (identifying nodes, edges, regions and their relationships), the system prepares the data in a format that can be reliably validated by verification tools, ensuring both energy efficiency and validation capability.
3Manufacturing precision
If multi-beam mask writers are used to write curvilinear patterns, then lithographic quality improves, but the mask making process becomes more complex
Solution Approach 1:
The patent applies segmentation by breaking down complex curvilinear patterns into discrete topological elements (nodes, edges, regions) that can be independently verified. This segmentation approach simplifies the verification of mask patterns by treating them as composable topological units rather than continuous geometric shapes, reducing the complexity of mask making verification.
Data Source
AI summary
A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.