Photonic Engine Packaging on Interposer Surfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current high bandwidth networking architectures face limitations in scaling due to the limited area around integrated circuits (ICs) for packaging photonic engines, leading to increased distance and power losses between ICs and photonic engines, which restricts future bandwidth density and power efficiency.
Innovation Solution
The solution involves packaging photonic engines on both the top and bottom surfaces of an interposer with increased stand-off heights and offset sockets to minimize interconnect distance, allowing for additional photonic engines and improved thermal and mechanical components, thereby reducing power consumption and enhancing bandwidth density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If photonic engines are packaged on the same surface of an interposer as the IC, then packaging area utilization is improved, but bandwidth density scaling is limited due to perimeter area constraints
Solution Approach 1:
The patent transitions from packaging photonic engines on a single two-dimensional surface to utilizing both top and bottom surfaces of the interposer. This dimensional expansion effectively doubles the available packaging area for photonic engines, enabling greater bandwidth density scaling while maintaining compact form factor.
2Productivity
If additional photonic engines are placed on the system board to increase bandwidth, then bandwidth capacity is improved, but power consumption increases due to longer interconnect distances
Solution Approach 1:
By packaging photonic engines on both surfaces of the interposer, the patent maintains short interconnect distances between the IC and photonic engines. This vertical stacking approach eliminates the need for long horizontal interconnects across the system board, thereby reducing power consumption while achieving high bandwidth capacity.
Solution Approach 2:
The patent combines the IC and multiple photonic engines into a single integrated package on the interposer. This merging of components minimizes interconnect distances and reduces the number of interconnect paths, thereby lowering power consumption while maintaining high bandwidth capacity.
3Loss of energy
If photonic engines are stacked vertically over the IC, then interconnect distance is minimized reducing power losses, but manufacturing complexity increases
Solution Approach 1:
The patent employs vertical stacking of photonic engines over the IC on both surfaces of the interposer. This three-dimensional arrangement minimizes interconnect distances and reduces power losses, while the use of standard interposer technologies keeps manufacturing complexity manageable.
Data Source
AI summary
Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.