Photonic IC Bridge Assembly for High-I/O Chip Integration
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Solution Overview
Problem
Existing methods for electrically connecting photonic integrated circuits (PICs) with silicon-based electrical integrated circuits (EICs) face challenges such as the need for external ceramics or Ball Grid Array (BGA) substrates, limited I/O interfaces due to top surface arrangement, and issues with signal integrity related to parasitic capacitance and impedance mismatches.
Innovation Solution
The proposed solution involves an optoelectronic assembly that includes a PIC and an EIC coupled through an interposer embedded in a mold compound, with bridging electrical connections established between the PIC and the interposer, allowing for direct electrical connection without the need for wire bonding or external substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect photonic chip and electrical chip to shared substrate, then electrical connection is established, but device complexity increases due to requirement of external ceramics or BGA substrates with VIAs
Solution Approach 1:
The patent extracts and eliminates the external substrate (ceramics or BGA) from the system by implementing direct bonding between photonic and electrical chips. The bonding pads are integrated directly onto the chip surfaces, removing the need for separate substrate structures with VIAs and trace routing.
Solution Approach 2:
The patent merges the functions of the substrate and the chip interconnection by implementing direct bonding between chips. The bonding interface integrates electrical connection, mechanical support, and signal routing in a single direct bond interface, eliminating the need for separate substrate components.
2Reliability
If wire bonding is used to connect photonic chip and electrical chip, then electrical connection is established, but the number of I/O interfaces is limited due to top surface arrangement
Solution Approach 1:
The patent transitions from top-surface wire bonding to edge-face bonding geometry. By arranging bonding pads on the lateral edges and faces of the chips rather than solely on the top surface, the design enables three-dimensional interconnection patterns that dramatically increase the number of available I/O interfaces.
3Reliability
If wire bonding is used for interconnection, then electrical connection is established, but signal integrity deteriorates due to parasitic capacitance, mutual inductance and impedance mismatches
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a direct solid-state bond interface. This substitution eliminates the long, thin wire interconnects that create parasitic inductance and capacitance, replacing them with a rigid, low-inductance bonded interface that maintains signal integrity at high speeds.
4Ease of manufacture
If solutions without wire bonding are used to connect photonic chip to electrical chip, then production cost is reduced, but PIC size must be large to provide sufficient surface area for connections
Solution Approach 1:
The patent uses edge-face bonding geometry to connect chips vertically and laterally rather than requiring large top-surface areas. This dimensional approach allows sufficient bonding area to be achieved through the chip edges and side faces, enabling direct bonding without requiring oversized photonic integrated circuits.
Data Source
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Figure 3A
AI summary
An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.