Photonic IC Packaging Architecture for Dense Interconnects
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Solution Overview
Problem
Packaging photonic integrated circuits (PICs) poses challenges due to the need for parallel tight-pitch interconnects for high-density, high-bandwidth electrical communication and optical access, with existing architectures consuming substantial PIC area and limiting electrical interconnect density.
Innovation Solution
A photonic packaging architecture that includes a package substrate, IC, insulating material, PIC with an active side, and optical lens coupled to the PIC's lateral side, with a substantial portion of the active side in contact with the insulating material, enabling electrical coupling to the substrate and IC, and using high-density flip-chip interconnects for efficient signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional PIC packaging architecture is used, then optical access is provided, but electrical interconnect density is limited and PIC area consumption is substantial
Solution Approach 1:
The patent transitions from planar interconnect arrangements to a three-dimensional stacked architecture where electronic ICs and photonic PICs are vertically integrated across multiple layers. This dimensional change enables significantly higher interconnect density by utilizing the vertical space above and below the PIC active area, rather than being constrained to the two-dimensional chip surface.
Solution Approach 2:
The patent implements a nested structure where electronic ICs are positioned both below (in cavities) and above the photonic PIC, with insulating material nested around the PIC to provide electrical isolation. This nested arrangement allows multiple functional components to occupy overlapping spatial volumes, maximizing space utilization and interconnect density while minimizing the overall footprint.
2Productivity
If parallel tight-pitch interconnects are implemented for high-density electrical communication, then bandwidth is improved, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent divides the interconnect system into multiple independent layers and modules, with each layer handling specific interconnect functions. This segmentation allows each layer to be manufactured and aligned independently, reducing the cumulative alignment complexity that would arise from attempting to create all interconnects in a single planar layer.
Solution Approach 2:
The patent introduces insulating material as an intermediary substance that provides both electrical isolation and mechanical positioning for the PIC and ICs. This intermediary layer simplifies alignment by providing a stable reference plane and reducing the need for ultra-precise direct alignment between conductive elements, thereby enabling high-density interconnects with relaxed manufacturing tolerances.
3Quantity of substance
If larger PIC footprint is used, then more interconnects can be accommodated, but power consumption increases and integration density decreases
Solution Approach 1:
By moving interconnects into the vertical dimension through stacked IC-PIC-IC architecture, the patent achieves high interconnect counts without increasing the lateral footprint of the PIC. This reduces the overall device area, which directly lowers power consumption and improves integration density while maintaining or increasing the number of available interconnects.
Solution Approach 2:
The patent merges electronic and photonic functions into a single integrated package structure, where electronic ICs and photonic PICs are vertically combined with shared interconnect resources. This merging eliminates the need for separate packaging and interconnection systems, reducing overall power consumption and improving space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables smaller footprint, higher electrical interconnect density, and reduced power consumption while maintaining optical signal integrity, facilitating efficient communication between PICs and other electrical devices.
Implementation Method 1
an optical lens coupled to the PIC on the lateral side
Data Source
AI summary
Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include an integrated circuit (IC) in a first layer, wherein the first layer includes a substrate having a first surface, an opposing second surface, and a lateral surface substantially perpendicular to the first and second surfaces, wherein the substrate includes a waveguide between the first and second surfaces, and wherein and the IC is nested in a cavity in the substrate; a PIC in a second layer, wherein the second layer is on the first layer and an active surface of the PIC faces the first layer, and wherein the IC is electrically coupled to the active side of the PIC; and an optical component optically coupled to the active surface of the PIC and the waveguide in the substrate at the second surface.