Photonic IC Package Interconnect Layout for Low-Capacitance Chip Links
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Solution Overview
Problem
Conventional systems face limitations in connecting multiple chips with low latency and high speed data transfer, leading to significant power consumption and excessive latency due to inefficient data movement, which hampers the performance of artificial intelligence computing tasks.
Innovation Solution
A photonic interconnect platform featuring hybrid electro-photonic integrated circuit packages with modulators and photodetectors, enabling data encoding and decoding between electrical and optical signals, and utilizing compact electro-absorption modulators to reduce thermal interference and signal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional electrical interconnects are used for data transfer between chips, then data can be transmitted between nodes, but power consumption increases significantly and latency becomes excessive
Solution Approach 1:
The patent replaces conventional electrical interconnects with photonic interconnects that use optical signals instead of electrical signals for data transmission. This substitution of the transmission medium fundamentally reduces power consumption and latency by eliminating resistive heating and enabling faster signal propagation through optical waveguides, directly addressing the energy and time loss problems in conventional systems.
Solution Approach 2:
The patent changes the fundamental parameter of signal transmission from electrical to optical domain. By using photonic integrated circuits that manipulate light properties (wavelength, intensity, phase) instead of electrical properties (voltage, current), the system achieves lower power consumption and reduced latency, as optical signals can carry more data with less energy dissipation.
2Length of moving object
If modulators are positioned close to active electronic elements in the EIC, then electrical signal lines can be made short, but thermal loading on the modulators increases significantly
Solution Approach 1:
The patent introduces thermal management intermediaries such as heat sinks, thermal vias, and thermally conductive materials between the modulators and the hot active electronic elements. These intermediaries act as thermal pathways that conduct heat away from the modulators, allowing them to be positioned close to active elements for short signal lines while preventing excessive thermal loading through efficient heat dissipation.
Solution Approach 2:
The patent segments the thermal management function from the electrical interconnect function by introducing separate thermal pathways (thermal vias, heat sinks) distinct from the electrical signal lines. This segmentation allows the modulators to be thermally isolated from hot electronic elements while maintaining short electrical connections, resolving the conflict between signal line length and thermal loading.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for low latency, high bandwidth data routing with reduced power consumption and signal interference, suitable for intra- and inter-chip connections, particularly beneficial for artificial neural networks.
Implementation Method 1
The package encodes data from electrical signals into optical signals by modulating the optical signals using the modulators
Implementation Method 2
The package encodes data from optical signals into electrical signals using the photodetectors
Implementation Method 3
The PIC also includes waveguides for guiding optical signals to and from the modulators and to the photodetectors
Implementation Method 4
the modulators are electro-absorption modulators (EAMs), e.g., EAMs formed in germanium silicon
Data Source
AI summary
A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.