Photonic Semiconductor Package Layout for Reliable PIC-EIC Integration
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Solution Overview
Problem
There is a need for improved semiconductor packages that integrate photonic integrated circuits (PIC) and electronic integrated circuits (EIC) with enhanced reliability and simplified manufacturing processes, while addressing the challenges of miniaturization and multi-functionality in electronic components.
Innovation Solution
A semiconductor package design that includes a photonic integrated circuit (PIC) chip and an electronic integrated circuit (EIC) chip, with a multi-insulating layer and a transparent support layer, and a manufacturing method that involves forming a first and second insulating layer to surround the chips, and a microlens to optimize optical coupling, enhancing reliability and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips (PIC and EIC) are integrated in a single semiconductor package to achieve multi-functionality, then the device functionality is improved, but the package complexity increases
Solution Approach 1:
The patent combines PIC chip and EIC chip into a single optical engine unit package, merging multiple functional components (photonic integrated circuit, electronic integrated circuit, insulating layers, support structures) into one integrated package. This merging approach achieves multi-functionality while managing complexity through unified structural design rather than separate discrete components.
Solution Approach 2:
The patent implements a nested structure where the EIC chip is positioned on top of the PIC chip, and multiple insulating layers are nested between and around these chips. The support layer is nested at the base, creating a compact hierarchical arrangement that integrates multiple functions within a confined space, reducing overall package complexity.
2Reliability
If insulating layers are added to surround the chips to improve reliability, then the package reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent combines multiple insulating functions into a unified multi-insulating layer structure that surrounds both PIC and EIC chips. Instead of applying separate insulating treatments to each chip individually, the design merges the insulation approach into a single integrated layer system, improving reliability while simplifying the manufacturing process.
Solution Approach 2:
The multi-insulating layer serves multiple functions simultaneously: electrical insulation between chips, mechanical support, and structural alignment. This multi-functional insulating layer reduces the need for separate components and processes, improving reliability without proportionally increasing manufacturing complexity.
3Volume of moving object
If the package size is reduced to meet miniaturization demands, then the form factor is improved, but the integration difficulty increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, placing the EIC chip vertically on top of the PIC chip. This dimensional change allows compact integration of multiple chips within a reduced footprint area, achieving miniaturization while managing integration complexity through vertical stacking rather than horizontal expansion.
Solution Approach 2:
The nested arrangement of chips and insulating layers creates a compact hierarchical structure that maximizes space utilization. By nesting the EIC chip within the vertical space above the PIC chip and inserting insulating layers between them, the design achieves miniaturization while organizing complex integration into a structured, manageable configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and simplifies the manufacturing process of semiconductor packages by optimizing optical coupling and reducing warpage, thereby enhancing the performance and integration of PIC and EIC chips.
Implementation Method 1
a microlens overlapping with the optic path block
Data Source
AI summary
A semiconductor package including a package substrate; an intermediate substrate on the package substrate; an optical engine unit on the intermediate substrate; a logic device adjacent to the optical engine unit and on the intermediate substrate; and a memory device adjacent to the logic device and on the intermediate substrate, wherein the optical engine unit includes a first redistribution substrate, a photonic integrated circuit (PIC) chip on the first redistribution substrate, an electronic integrated circuit (EIC) chip on the PIC chip, a multi-insulating layer surrounding the PIC chip and the EIC chip, and a transparent support layer on the EIC chip and the multi-insulating layer.