Photonic Semiconductor Package Layout for Short-Path Signal Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in preventing failures in photonic integrated circuit (PIC) chips and achieving efficient signal transmission over short distances.
Innovation Solution
The semiconductor package design includes a package substrate with a first waveguide, a PIC chip with a second waveguide, a first molding layer surrounding the PIC chip, an electronic integrated circuit (EIC) chip overlapping the PIC chip, and a semiconductor chip on the PIC chip, with stack structures arranged horizontally to enhance signal transmission and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PIC chip is mounted on the package substrate with waveguides for optical signal transmission, then the functionality and integration of the semiconductor package is improved, but the risk of failure in the PIC chip increases due to exposure to harmful factors
Solution Approach 1:
A molding layer is formed to surround the PIC chip before it fails, providing protective cushioning against harmful factors such as moisture, oxygen, and mechanical stress. This preventive encapsulation shields the vulnerable PIC chip while maintaining its optical transmission functionality through the waveguide structure.
2Reliability
If the signal transmission distance is reduced to improve reliability, then the stability of signal transmission is improved, but the structural complexity of the package increases
Solution Approach 1:
The package structure transitions to a three-dimensional stacked configuration where the PIC chip is vertically positioned above the package substrate with waveguides extending in the vertical dimension. This vertical stacking reduces horizontal signal transmission distance while organizing multiple components (EIC chip, molding layer, stack structures) in the vertical dimension, thereby improving signal reliability without excessive horizontal complexity.
3Quantity of substance
If multiple components including EIC chip and stack structures are arranged on the molding layer, then the integration density is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The package structure is segmented into distinct functional layers: the package substrate with waveguides at the bottom, the molding layer surrounding the PIC chip in the middle, and the EIC chip and stack structures arranged on top of the molding layer. This segmentation allows each component to be manufactured and positioned independently with standard precision, reducing the cumulative precision requirements compared to a fully integrated single-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents failures in PIC chips and improves signal transmission reliability over short distances by optimizing the arrangement of waveguides, molding layers, and integrated circuits within the semiconductor package.
Implementation Method 1
a first waveguide disposed on an upper surface of the package substrate, and a second waveguide disposed on a lower surface of the PIC chip
Data Source
AI summary
A semiconductor package includes a package substrate including a first waveguide, a PIC chip on the package substrate and including a second waveguide, a first molding layer on the package substrate and surrounding the PIC chip, an electronic integrated circuit (EIC) chip arranged on the first molding layer and the PIC chip to vertically overlap both the first molding layer and the PIC chip, a semiconductor chip on the PIC chip, and a plurality of stack structures arranged horizontally apart from each other on the first molding layer and the PIC chip, wherein the first waveguide is disposed on an upper surface of the package substrate, and wherein the PIC chip is arranged on the package substrate such that a surface of the PIC chip, adjacent to the second waveguide, faces the package substrate.