Photonic Package Pillar Fabrication via CMP Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current photonic package devices face challenges in efficient fabrication, particularly in achieving uniform pillar size and height, and sharp profile of embedding holes due to complex photomask requirements and high topography issues during the manufacturing process.
Innovation Solution
A method involving a CMP process after forming the pillar pattern allows for a photomask to be formed on a flat surface, reducing photomask complexity and enabling three-step etching to transfer patterns from the top silicon to the base substrate, along with defining pillar patterns during waveguide structure formation to save photomasks and improve etching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex photomask requirements are used to achieve uniform pillar size and height, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the pillar pattern during the waveguide structure formation process itself, rather than requiring separate photomask steps. This preliminary integration of pillar definition into the existing waveguide fabrication process eliminates the need for additional complex photomasks while achieving uniform pillar dimensions through the self-aligned nature of the process
Solution Approach 2:
The patent merges the pillar formation process with the waveguide structure formation process. By combining these two operations into a single fabrication sequence, the patent reduces the total number of photomasks required while maintaining manufacturing precision for both the waveguides and pillars through a unified process approach
2Manufacturing precision
If multiple photomask steps are used to form pillar patterns, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent combines pillar pattern formation with waveguide structure formation into a single etching step, eliminating multiple sequential photomask operations. This merging maintains etching precision through self-alignment while significantly improving fabrication efficiency by reducing the total number of process steps and photomask changes required
3Device complexity
If high topography issues are present during manufacturing, then device complexity increases, but ease of manufacture worsens
Solution Approach 1:
The patent performs preliminary planarization by forming the pillar pattern at the same elevation level as the waveguide structures during the initial fabrication process. This preliminary action prevents the development of high topography issues that would otherwise require additional planarization steps, thereby improving ease of manufacture for subsequent photomask coating operations while maintaining structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach addresses issues of poor coating and corner damage, achieving uniform pillar sizes and heights, and results in a reliable process for forming photonic package devices with improved structural integrity and efficiency.
Implementation Method 1
A method involving a CMP process after forming the pillar pattern allows for a photomask to be formed on a flat surface
Implementation Method 2
enabling three-step etching to transfer patterns from the top silicon to the base substrate
Data Source
AI summary
A method for fabricating a photonic package device is provided. The method includes patterning a semiconductor layer of a semiconductor-on-insulator (SOI) substrate into a waveguide structure and at least one first semiconductor pillar; forming a metal-dielectric stack over the waveguide structure and the first semiconductor pillar; etching an opening in the metal-dielectric stack to expose the first semiconductor pillar; etching an insulator layer of the SOI substrate to form at least one insulator cap below the first semiconductor pillar; and etching a base semiconductor substrate of the SOI substrate to form at least one second semiconductor pillar below the insulator cap.