Photonics Chip Calibration Markers for Precise Metrology

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Solution Overview

Problem

The accuracy of metrology tools in measuring dimensions of photonic structures on photonics chips is contingent upon the calibration quality, necessitating improved structures and methods for precise calibration.

Innovation Solution

Incorporation of calibration markers adjacent to photonic structures, featuring predetermined dimensions, allows for accurate calibration of metrology tools by converting pixel measurements to linear dimensions using a calibration factor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a metrology tool is used to measure photonic structure dimensions, then measurement capability is provided, but measurement precision is insufficient without proper calibration

Engineering Contradiction:
Improvemeasurement precisionVSAvoidcalibration quality
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The calibration marker is fabricated together with the photonic structure during the back-end-of-line stacking process, establishing a known reference dimension before metrology measurements are performed. This preliminary action ensures that the metrology tool can be calibrated against a trusted reference that is inherently tied to the fabrication process, thereby improving measurement precision without compromising reliability.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If calibration markers are added to the photonics chip structure, then measurement accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvemeasurement accuracyVSAvoidstructure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The calibration marker is merged with the photonic structure by fabricating both features simultaneously during the back-end-of-line stacking process. The calibration marker is formed as part of the same interlayer dielectric stack and is surrounded by the same fill features, thereby integrating the calibration function into the existing device structure without adding separate calibration components or processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The calibration marker serves dual purposes: it functions as both a structural element of the photonic device and as a self-contained calibration reference. The marker's predetermined dimension is established through the same fabrication processes that create the photonic structure, allowing the device to self-calibrate without requiring external calibration standards or additional measurement infrastructure.

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If multiple back-end-of-line stacks are formed with fill features, then manufacturing completeness is achieved, but identification of calibration areas becomes difficult

Engineering Contradiction:
Improvemanufacturing completenessVSAvoidcalibration area identification
Core Design Contradiction:
Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

The calibration marker is distinguished from surrounding fill features by creating an asymmetric pattern: while fill features surround the calibration marker on all sides, the marker itself has a different geometric configuration or material composition that makes it visually distinct in metrology images. This asymmetric design allows automated detection algorithms to easily identify the calibration area amidst the symmetric array of fill features, reducing detection difficulty without compromising manufacturing completeness.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12449615B2Calibration markers for a photonics chip
Publication Date: 2025.10.21 GLOBALFOUNDRIES US INC
  • US12449615B2 patent drawing
  • US12449615B2 patent drawing
  • US12449615B2 patent drawing

AI summary

Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.