Photonics Chip Layout for FDSOI Transistor and Optical Integration
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Solution Overview
Problem
Conventional photonics chips using silicon-on-insulator substrates face limitations in integrating fully-depleted silicon-on-insulator field-effect transistors due to restrictions on device layer thickness and inadequate electrical isolation for back-gate control, which impede the performance of optical components.
Innovation Solution
A photonics chip structure with a substrate having a thin device layer (4-20 nm) and a buried insulator layer (5-40 nm) is developed, allowing for the formation of fully-depleted silicon-on-insulator field-effect transistors and optical components, with a step height transition between regions to minimize optical loss and enable back-gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick device layer is used in conventional silicon-on-insulator substrates, then optical component performance is improved, but fully-depleted field-effect transistors cannot be integrated
Solution Approach 1:
The device layer is segmented into two distinct layers: a first device layer with thickness of 4-20 nm for transistor formation, and a second device layer with greater thickness for optical component formation. This segmentation allows each layer to be optimized independently for its specific function, enabling both fully-depleted transistors and high-performance optical components to coexist on the same substrate.
Solution Approach 2:
Different regions of the substrate are assigned different device layer thicknesses tailored to specific functions: thin device layers (4-20 nm) in transistor regions to enable full depletion, and thick device layers in optical regions to maintain optical performance. This local optimization resolves the contradiction by allowing each component type to have the ideal thickness for its operation.
2Reliability
If the buried oxide layer thickness is increased to provide adequate electrical isolation, then back-gate control capability is improved, but device layer thickness flexibility is reduced
Solution Approach 1:
The device layer segmentation into thin first layer and thick second layer allows the buried oxide layer to maintain adequate thickness for electrical isolation and back-gate control, while the overall device structure achieves the thin effective channel thickness needed for fully-depleted transistor operation. The segmented structure provides the flexibility to optimize both isolation and transistor performance.
Data Source
AI summary
Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.