Photoreceiving Buffer Circuit Offset Voltage Stability

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Solution Overview

Problem

Existing photoreceiving ICs experience varying offset voltage due to differences in collector-emitter voltages caused by power supply voltage variations, leading to dependence on power supply voltage.

Innovation Solution

A buffer circuit configuration is introduced, featuring transistors with base connections to a power supply, constant current circuits, and mirror circuits that equalize collector currents and set operating point voltages, reducing collector-emitter voltage differences and power supply voltage dependence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a current mirror circuit is used to equalize collector currents, then the offset voltage is reduced, but the offset voltage becomes dependent on power supply voltage variations due to differences in collector-emitter voltages

Engineering Contradiction:
Improveoffset voltageVSAvoidpower supply voltage dependence
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies equipotentiality by ensuring that the collector-emitter voltages of transistors in the current mirror circuit are equalized. Specifically, the circuit configuration ensures that Vce1 = Vce2 through proper biasing and connection arrangements, thereby eliminating the Early voltage effect that causes offset voltage drift with power supply variations. This makes the offset voltage stable and independent of power supply voltage changes.

Inventive Principle:
Principle #12Equipotentiality

2Stability of the object's composition

If the collector voltage is fixed to eliminate offset voltage, then offset stability improves, but the circuit loses adaptability to power supply voltage variations

Engineering Contradiction:
Improveoffset voltage stabilityVSAvoidpower supply voltage adaptability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the collector voltage adaptive rather than fixed. The circuit allows the collector voltage to dynamically adjust in response to power supply voltage variations while maintaining the equality of collector-emitter voltages across transistors. This dynamic adjustment ensures that Vce remains equal throughout operating conditions, providing both stability and adaptability.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively eliminates differences in collector-emitter voltages due to power supply variations, resulting in reduced power supply voltage dependence of the offset voltage, maintaining stable offset voltage characteristics even with power supply changes.

Implementation Method 1

a photoreceiving device and converts it into a voltage signal in a current-voltage conversion circuit

Methodology Applied
Scientific EffectPhotoelectric Effect: Photoelectric Effect

Data Source

PatentUS7944249B2Photoreceiving circuit
Publication Date: 2011.05.17 RENESAS ELECTRONICS CORP
  • US7944249B2 patent drawing
  • US7944249B2 patent drawing
  • US7944249B2 patent drawing

AI summary

A buffer circuit includes a first transistor (T1) having a base connected to a first power supply, the emitter (E1) and collector (C1) connected as input and output nodes, a second transistor (T2) having a base connected to the first power supply, a first constant current circuit using a difference between outgoing current from E1 and an input current at the current signal input node as a constant current, and determining outgoing current from the emitter of T2 equal to the constant current; and a first mirror circuit equalizing first and second collector currents with a third transistor (T3) with C1 and a fourth transistor (T4) with a collector connected to a collector of T2, a first operating point voltage is provided to the current signal output node between T3 and T1, and a second operating point voltage based on the first operating point voltage between T4 and T2.