Photoresist Additive Coating to Reduce Lithography Reflection
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining functionality, as traditional bonding processes are inefficient and require complex techniques.
Innovation Solution
A method involving a carrier substrate with an adhesive layer, a polymer layer, and a seed layer, where vias are formed using a photoresist and electroplating, allowing for the stacking and bonding of semiconductor devices with improved protection and connectivity through redistribution layers and passivation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional bonding processes are used to bond semiconductor devices, then bonding functionality is achieved, but the process complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The patent introduces a carrier substrate with an adhesive layer as an intermediary component between the semiconductor die and the final package structure. This carrier substrate simplifies the bonding process by providing a pre-prepared bonding surface with adhesive properties, eliminating the need for complex direct bonding techniques between semiconductor devices. The adhesive layer acts as a mediator that facilitates easy attachment while reducing process complexity.
2Productivity
If semiconductor device size is reduced to increase integration density, then more devices can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the semiconductor packaging process into distinct functional layers: carrier substrate, adhesive layer, semiconductor die, and overmold layer. This segmentation allows each component to be optimized and manufactured separately with standard precision requirements, then assembled together. The carrier substrate with its adhesive layer provides a stable platform that accommodates small semiconductor dies without requiring the entire packaging process to achieve ultra-high precision.
Solution Approach 2:
The adhesive layer serves as an intermediary that compensates for dimensional variations and alignment tolerances. It provides a compliant bonding interface that can accommodate slight misalignments and thermal expansion differences, thereby maintaining bonding reliability even when working with smaller, more densely integrated semiconductor devices that have tighter dimensional tolerances.
3Adaptability or versatility
If sophisticated bonding techniques are used to bond separate substrates, then stacked semiconductor devices can be formed, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by pre-coating the carrier substrate with an adhesive layer before mounting the semiconductor die. This pre-prepared bonding surface eliminates the need for complex bonding techniques during the assembly process. The adhesive layer is applied in advance, allowing for simple pick-and-place mounting of the die without requiring sophisticated real-time bonding equipment or processes.
Solution Approach 2:
The adhesive layer acts as an intermediary bonding medium that enables straightforward attachment of the semiconductor die to the carrier substrate. This intermediary approach replaces sophisticated direct bonding techniques (such as eutectic bonding or anodic bonding) with a simpler adhesive-based process, thereby reducing manufacturing complexity while still enabling stacked device configurations.
4Productivity
If minimum feature size is continuously reduced, then integration density improves, but device vulnerability to manufacturing defects increases
Solution Approach 1:
The patent segments the device structure into distinct functional layers with the semiconductor die mounted on a carrier substrate. This segmentation isolates the small, vulnerable feature structures within the die from the packaging process, allowing the die to be manufactured with high precision in a controlled environment. The carrier substrate and overmold provide mechanical protection and environmental isolation, thereby enhancing reliability without compromising integration density.
Solution Approach 2:
The adhesive layer and overmold structure provide beforehand cushioning by creating a protective encapsulation around the semiconductor die. This protective structure absorbs mechanical stresses, thermal stresses, and environmental damage before they can reach the vulnerable small features on the die surface, thereby maintaining reliability even as feature sizes are reduced to increase integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more efficient semiconductor devices with enhanced protection and connectivity, facilitating the integration of multiple semiconductor devices into a single package with reduced manufacturing complexity.
Implementation Method 1
vias are formed using a photoresist and electroplating
Implementation Method 2
vias are formed using a photoresist and electroplating
Implementation Method 3
a carrier substrate with an adhesive layer
Data Source
AI summary
A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti -reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.